CoreSight ETM‑R4 Technical Reference Manual: 3.4.1. Functional grouping of registers

3.4.1. Functional grouping of registers

This section lists the macrocell registers by functional group, as follows:

These functional groups include all of the registers.

General control and ID registers

Table 3.2 lists the general control and ID registers in register number order.

Table 3.2. General control and ID registers

Register number	Name	Base offset	Clock domain	Description
`0x000`	ETM Control	`0x000`	CLK	ETM Main Control Register
`0x001`	Configuration Code	`0x004`	CLK	Configuration Code Register
`0x003`	ASIC Control	`0x00C`	CLK	ASIC Control Register
`0x004`	ETM Status	`0x010`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x005`	System Configuration	`0x014`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x00B`	FIFOFULL Level^[a]	`0x02C`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x078`	Synchronization Frequency	`0x1E0`	CLK	Embedded Trace Macrocell Architecture Specification.^[b]
`0x079`	ETM ID	`0x1E4`	CLK	ETM ID Register
`0x07A`	Configuration Code Extension	`0x1E8`	CLK	Configuration Code Extension Register
`0x080`	CoreSight Trace ID	`0x200`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x0C5`	Power-Down Status	`0x314`	CLK	Power-Down Status Register
^[a]Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level where data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification. ^[b]Only bits[11:2] of the Synchronization Frequency Register are implemented. Bits[1:0] Read-As-Zero.

TraceEnable and ViewData registers

Table 3.3 lists the TraceEnable and ViewData registers in register number order.

Table 3.3. TraceEnable and ViewData registers

Register number	Name	Base offset	Clock domain	Description
`0x006`	TraceEnable Start/Stop Resource control	`0x018`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x007`	TraceEnable Control 2	`0x01C`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x008`	TraceEnable Event	`0x020`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x009`	TraceEnable Control 1	`0x024`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x00C`	ViewData Event	`0x030`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x00D`	ViewData Control 1	`0x034`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x00F`	ViewData Control 3	`0x03C`	CLK	Embedded Trace Macrocell Architecture Specification.

Comparator registers

Table 3.4 lists the Comparator registers in register number order. These control the Address, Data and Context ID comparators.

Table 3.4. Comparator registers

Register number	Name	Base offset	Clock domain	Description
`0x010` to `0x017`	Address Comparator Value 1 - 8	`0x040` to `0x05F`	CLK	Embedded Trace Macrocell Architecture Specification
`0x020` to `0x027`	Address Comparator Access Type 1 - 8	`0x080` to `0x09F`	CLK	Embedded Trace Macrocell Architecture Specification^[a]
`0x030` ^[b]	Data Comparator Value 1 ^[b]	`0x0C0` ^[b]	CLK	Embedded Trace Macrocell Architecture Specification
`0x032` ^[b]	Data Comparator Value 3 ^[b]	`0x0C8` ^[b]	CLK	Embedded Trace Macrocell Architecture Specification
`0x040` ^[b]	Data Comparator Mask 1 ^[b]	`0x100` ^[b]	CLK	Embedded Trace Macrocell Architecture Specification
`0x042` ^[b]	Data Comparator Mask 3 ^[b]	`0x108` ^[b]	CLK	Embedded Trace Macrocell Architecture Specification
`0x06C`	Context ID Comparator Value	`0x1B0`	CLK	Embedded Trace Macrocell Architecture Specification
`0x06F`	Context ID Comparator Mask	`0x1BC`	CLK	Embedded Trace Macrocell Architecture Specification
^[a]Because the Cortex-R4 processor does not implement the Security Extensions, only bits[9:0] of the Address Comparator Access Type Registers are implemented. ^[b]In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM-R4, reserved areas are: Register `0x031`, Data Comparator Value 1, at offset `0x0C4` Register `0x033`, Data Comparator Value 3, at offset `0x0CC` Register `0x041`, Data Comparator Mask 1, at offset `0x104` Register `0x043`, Data Comparator Mask 3, at offset `0x10C`. You must not write to these reserved register addresses. The value of a reads from these addresses is Unknown.

Counter, Sequencer and other resource registers

Table 3.5 lists the Counter, Sequencer and other resource registers in register number order. These control:

the two Counters, and associated events
the Sequencer, and associated state change events
Trigger events
EXTOUT (External Output) events
Extended External Input selection.

Table 3.5. Counter, Sequencer and other resource registers

Register number	Name	Base offset	Clock domain	Description
`0x002`	Trigger Event	`0x008`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x050`, `0x051`	Counter Reload Value 1 - 2	`0x140`, `0x144`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x054`, `0x055`	Counter Enable Event 1 - 2	`0x150`, `0x154`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x058`, `0x059`	Counter Reload Event 1 - 2	`0x160`, `0x164`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x05C`, `0x05D`	Counter Value 1 - 2	`0x170`, `0x174`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x060` to `0x065`	Sequencer State Transition Events	`0x180` to `0x194`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x067`	Current Sequencer State	`0x19C`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x068`, `0x069`	External Output Event 1 - 2	`0x1A0`, `0x1A4`	CLK	Embedded Trace Macrocell Architecture Specification.
`0x07B`	Extended External Input Selector	`0x1EC`	CLK	Extended External Input Selection Register.

CoreSight Management registers

Table 3.6 lists the CoreSight Management registers in register number order.

Table 3.6. CoreSight Management registers

Register number	Name	Base offset	Clock domain	Description
`0x3C0`	Integration Mode Control	`0xF00`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3E8`	Claim Tag Set	`0xFA0`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3E9`	Claim Tag Clear	`0xFA4`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3EC`	Lock Access	`0xFB0`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3ED`	Lock Status	`0xFB4`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3EE`	Authentication Status	`0xFB8`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3F2`	Device Configuration	`0xFC8`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3F3`	Device Type	`0xFCC`	PCLKDBG	Embedded Trace Macrocell Architecture Specification
`0x3F4` to `0x3F7`	Peripheral ID4 to 7	`0xFD0` to `0xFDC`	PCLKDBG	Peripheral Identification Registers
`0x3F8` to `0x3FB`	Peripheral ID0 to 3	`0xFE0` to `0xFEC`	PCLKDBG	Peripheral Identification Registers
`0x3FC` to `0x3FF`	Component ID0 to 3	`0xFF0` to `0xFFC`	PCLKDBG	Component Identification Registers

Integration Test registers

Table 3.7 lists the Integration Test registers in register number order.

Table 3.7. Integration Test registers

Register number	Name	Base offset	Clock domain	Description
`0x3B6`	ITETMIF	`0xED8`	CLK	Processor-ETM Interface Register
`0x3B7`	ITMISCOUT	`0xEDC`	CLK	Miscellaneous Outputs Register
`0x3B8`	ITMISCIN	`0xEE0`	CLK	Miscellaneous Inputs Register
`0x3B9`	ITTRIGGERACK	`0xEE4`	ATCLK	Trigger Acknowledge Register
`0x3BA`	ITTRIGGERREQ	`0xEE8`	ATCLK	Trigger Request Register
`0x3BB`	ITATBDATA0	`0xEEC`	ATCLK	ATB Data Register 0
`0x3BC`	ITATBCTR2	`0xEF0`	ATCLK	ATB Control Register 2
`0x3BD`	ITATBCTR1	`0xEF4`	ATCLK	ATB Control Register 1
`0x3BE`	ITATBCTR0	`0xEF8`	ATCLK	ATB Control Register 0

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