A 32-bit wide ATB, used for trace output from the macrocell. Up to four bytes of trace packet information can be transferred over the bus in one clock cycle. This interface has hand shaking signals that indicate when trace data is valid and when the receiving component is ready to accept data. There are also signals to request and acknowledge a flush of the trace information and to indicate when a trigger condition has occurred.

See the AMBA 3 ATB Protocol Specification for more information about this interface.

An APB that provides access to the programmable registers in the ETM-R4 and connects to the system Debug APB. This interface is used to configure the ETM-R4 for a trace session.

See the AMBA 3 APB Protocol Specification for more information about this interface.

The Cortex-R4 passes its execution information to ETM-R4 over this interface. This interface is divided into two main sections for instruction and data execution information.

The instruction section contains instruction address and control information. The information carried on the control bus includes:

The data section contains address, data and control information. The address bus carries the addresses of memory locations accessed by load and store instructions. The data bus is 64-bits wide and carries the data values transferred by load, store and coprocessor register transfer instructions. The information carried by the control bus includes the type, direction and size of a data transfer. There is also a context ID bus that indicates the context ID value of the processor.

This interface also includes:

The ETM-R4 has other interface signals that:

This interface contains the scan enable and reset bypass signals used in production testing of the ETM-R4.