| System controller | APB peripheral. See Chapter 3 Programmer’s Model. |
| Dynamic Clock Generator (DCG) | Custom clock generator. See Intelligent Energy Management (IEM). |
| AXI ID merge block, Axi64IdMerge | Block created to reduce eight ID bits
to six to: Make better use of
PL340 Quality of Service (QoS) Reduce maximum ID width in SoC, the L2CC configuration
port can only accept eight ID bits. Cascaded AXI blocks require
nine bits. Reduce ID bit width on AXI master port.
See Chapter 2 Functional Overview. |
| Ring oscillators, RingOscGate | Ring oscillators created from gate delay elements
to measure voltage in Vsoc and Vcore domains. |
| SoC Configuration Capture Block, SoCConfig | SOC Config block added custom code. |
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