ARM1176JZF Development Chip Technical Reference Manual 3.3.2. Entering test mode

3.3.2. Entering test mode

Select test mode by setting the TESTMODE input HIGH. The configuration block is fully scan inserted to enable full control of the configuration inputs. Some configurations must however, be under user control or held static during test. For this purpose, the configuration block has test inputs that enable you to drive configurations directly. Table 3.2 lists the test mode configuration inputs.

Table 3.2. Test mode configuration inputs

Configuration signal	Description	RDATA[n] input sampled	Reset state	TESTMODE
CFGCOREID[3:0]	LS nibble of core ID[7:0]	[3:0]	4'h1	N/A
CFGREMAP[1:0]	Defines boot memory map: 00 = normal memory 01 = AXI ROM 10 = SMC 11 = AXI master port.	[5:4]	2'b01	N/A
CFGINITRAM	ITCM at `0x0` for data and instructions at reset	[6]	1'b0	N/A
CFGVINITHI	High exception vector location	[7]	1'b0	N/A
CFGBIGENDINIT	ARMv5 big endian behavior	[8]	1'b0	N/A
CFGUBITINIT	ARMv6 unaligned behavior	[9]	1'b1	N/A
CFGCP15SDISABLE	TZ write access disable	[10]	1'b0	N/A
CFGAXIRATIO	AXI: Core clock ratio: 0 = 2:1 1 = 4:1.	[11]	1'b0	1'b0
CFGAXIEXTRATIOSLV[2:0]	AXI external slave clock ratio: 000 = 1:1 001 = 2:1 010 = 3:1 011 = 4:1 100 = 5:1 101 = 6:1 110 = 7:1 111 = 8:1.	[14:12]	3'b111	TSTAXIEXTRATIOSLV
CFGAXIEXTRATIOMSTR[2:0]	AXI external master clock ratio: 000 = 1:1 001 = 2:1 010 = 3:1 011 = 4:1 100 = 5:1 101 = 6:1 110 = 7:1 111 = 8:1.	[17:15]	3'b111	TSTAXIEXTRATIOMSTR
CFGSMCAXIRATIO	SMC AXI sync down clock ratio: 0 = 1:1 1 = 2:1.	[18]	1'b0	1'b0
CFGSMCMEMRATIO[1:0]	SMC AXI to external memory clock ratio 00 = 1:1 01 = 2:1 10 = 3:1 11 = undefined.	[20:19]	2'b10	2'b00
CFGSMMWCS7[1:0]	SMC bank 7 data width 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = undefined.	[22:21]	2'b10	2'b00
CFGPLLREFCLK1		[23]	1'b0	TSTPLLREFCLK1
CFGPLLBYPASS		[24]	1'b0	TSTPLLBYPASS
CFGPLL1BYPASS		[25]	1'b0	TSTPLL1BYPASS
CFGPLL2BYPASS		[26]	1'b0	TSTPLL2BYPASS
CFGPLLFIXEDVCORANGE^[1]	Selects VCO range: HIGH > 133MHz LOW < 133MHz.	[27]	1'b1	TSTPLLFIXEDVCORANGE
CFGPLLFIXEDM^[1]	PLL feedback divider	[31:28]	4'h1	TSTPLLFIXEDM
CFGPLLFIXEDN^[1]	PLL input divider	[34:32]	3'b001	TSTPLLFIXEDN
CFGPLLFIXEDBYPASSEN^[1]	Bypasses VCO	[35]	1'b0	TSTPLLFIXEDBYPASSEN
CFGPLLFIXEDPLLEN^[1]	PLL Enable	[36]	1'b1	TSTPLLFIXEDPLLEN
CFGPLLFIXEDDESKEW^[1]	Selects external clock feedback path for on chip clock deskew	[37]	1'b1	TSTPLLFIXEDDESKEW
CFGIRQSOURCE	Selects the nIRQ, nFIQ source: 0 = external 1 = internal.	[38]	1'b1	-
CFGIEMSHUTDOWN	Selects the IEM subsystem to be powered down from reset: 0 = functional 1 = shutdown.	[39]	1'b0	-
CFGCLKSTOPSBWFI	Selects whether the Clock is stopped to the L2CC and ETM during CPU STANDBYWFI State: 0 = clock is left free running 1 = clock is stopped.	[40]	1'b1	-
^[1]You must disable the internal feedback and input dividers to use the PLL to de-skew the off-chip AXI interface to the on-chip SoC clock. You must also enable the PLL, not bypass the VCO, enable de-skew, and set the VCO range correctly to use PLL de-skew mode.

Copyright © 2007 ARM Limited. All rights reserved.	ARM DDI 0375A
Non-Confidential
PDF version