ARM1176JZF Development Chip Technical Reference Manual 3.7.2. Distributor Register descriptions

3.7.2. Distributor Register descriptions

This section describes the registers and contains the following subsections:

Distributor Register Control Register

Figure 3.19 shows the bit assignments for this register.

Figure 3.19. Distributor Register Control Register bit assignments

Table 3.20 lists the bit assignments for this register.

Table 3.20. Distributor Register Control Register bit assignments

Bits	Offset	Name	Type	Function
[31:1]	`0x000`		RW	Undefined, SBZ.
[0]	-	Enable	RW	Distributor enable. If this bit is 0, no interrupts are sent out of the distributor. Disabling the distributor while there are pending interrupts might give rise to spurious interrupts as a result of the inherent timing race between the disabling of the interrupt and the CPU response to pending interrupts.

Interrupt Controller Type Register

Figure 3.20 shows the bit assignments for this register.

Figure 3.20. Interrupt Controller Type Register bit assignments

Table 3.21 lists the bit assignments for this register.

Table 3.21. Interrupt Controller Type Register bit assignments

Bits	Offset	Name	Type	Function
[31:8]	`0x004`		RW	Undefined, SBZ
[7:5]	-	CPU number	RW	CPU number encoding for the ARM1176 development chip is:000: System contains 1 CPU.
[4:0]	-	IT lines number	RW	IT lines number encoding for the GIC in the ARM1176 development chip is as follows:00001: 64 interrupts support, 32 interrupt lines support.

You can use the number of IT lines to determine which sets of registers in the Distributor register map are populated. In the ARM1176JZF core, IT lines is hard-coded to 5'b00001, indicating 64 interrupt sources.

The CPU number is encoded as:

000: System contains 1 CPU.
001: System contains 2 CPUs.
010: System contains 3 CPUs.
011: System contains 4 CPUs.
0xx: Reserved for future extension.

Note

The CPU number indicates the number of CPUs in the system. The CPU number for the ARM 1176JZF development chip is always 1.

Interrupt Set-Enable Registers

These registers control an enable bit for each interrupt in the interrupt distributor.

The GIC in the chip supports 64 interrupts:

32 software interrupts
32 hardware interrupts.

Interrupt Set-Enable Register 0

Figure 3.21 shows the bit assignments for this register.

Figure 3.21. Interrupt Set-Enable Register 0 bit assignments

Table 3.22 lists the bit assignments for this register.

Table 3.22. Interrupt Set-Enable Register 0 bit assignments

Bits	Offset	Name	Type	Function
[31:29]	`0x100`	Interrupt enable	RW	Bit 31 is for the legacy nIRQ pin. Bit 30 is for a private watchdog in an MPCore system and is not used in this SoC. Bit 29 is for a private timer in an MPCore system and is not used in this SoC.
[28:16]		Interrupt enable	RO	Undefined interrupts, read as 0.
[15:0]		Interrupt enable	RO	Interrupts 0 to 15 are inter-processor, or reserved for software use. Read as 1.

Interrupt Set-Enable Register 1

Figure 3.22 shows the bit assignments for this register.

Figure 3.22. Interrupt Set-Enable Register 1 bit assignments

Table 3.23 lists the bit assignments for this register.

Table 3.23. Interrupt Set-Enable Register 1 bit assignments

Bits	Offset	Name	Type	Function
[31:0]	`0x104`	Interrupt enable	RW	Writing a 1 sets the interrupt enable bit and so, the interrupt is transmitted to the targeted CPU.

In these registers, writing a 1 sets the corresponding interrupt enable bit, and a read reads back a 1. When this is set, you can only clear it by using the Enable-Clear Register. In other words, writing a 0 to the Set-Enable Register does not write a 0 to the corresponding interrupt enable bit.

The values read in the Set-Enable Registers, for a particular range of interrupts, represent currently enabled interrupts. Non-present interrupts, depending on the Interrupt Number field of the Interrupt Controller Type Register related fields are read as zero, and writing to these fields has no effect.

Interrupt Clear-Enable Registers

These registers control an enable bit for each interrupt in the interrupt distributor. There can be up to eight Clear-Enable registers. Because the GIC in the ARM1176JZF Development Chip only supports 64 interrupts, it has two such registers and the rest are unused.

Interrupt Clear-Enable Register 0

Figure 3.23 shows the bit assignments for this register.

Figure 3.23. Interrupt Clear-Enable Register 0 bit assignments

Table 3.24 lists the bit assignments for this register.

Table 3.24. Interrupt Clear-Enable Register 0 bit assignments

Bits Offset Name Type Function

[31:29]

Bits	Offset	Name	Type	Function
[31:29]	`0x180`	Interrupt enable	RW	Writing a 1 clears the interrupt enable bit and it reads a 0. Bit 31 is for the legacy nIRQ pin. Bit 30 is for a private watchdog in an MPCore system and is not used in this SoC. Bit 29 is for a private timer in an MPCore system and is not used in this SoC.
[28:16]	-	Interrupt enable	RO	Undefined interrupts, read as 0.
[15:0]	-	Interrupt enable	RO	Interrupts 0 to 15 are inter-processor or reserved for software use. Read as 0.

0x180

Interrupt enable

Writing a 1 clears the interrupt enable bit and it reads a 0.

Bit 31 is for the legacy nIRQ pin.

Bit 30 is for a private watchdog in an MPCore system and is not used in this SoC.

Bit 29 is for a private timer in an MPCore system and is not used in this SoC.

[28:16] - Interrupt enable RO Undefined interrupts, read as 0.

[15:0] - Interrupt enable RO Interrupts 0 to 15 are inter-processor or reserved for software use. Read as 0.

Interrupt Clear-Enable Register 1

Figure 3.24 shows the bit assignments for this register.

Figure 3.24. Interrupt Clear-Enable Register 1 bit assignments

Table 3.25 lists the bit assignments for this register.

Table 3.25. Interrupt Clear-Enable Register 1 bit assignments

Bits	Offset	Name	Type	Function
[31:0]	`0x184`	Interrupt enable	RW	Writing a 1 clears the interrupt enable bit and it reads a 0.

Writing a 1 clears the corresponding interrupt enable bit and a read reads back a 0. When cleared, you can only set this bit by using the Set-Enable Register. In other words, writing a 1 to the Clear-Enable Register does not write a 1 to the corresponding interrupt enable bit.

The values read in the Clear-Enable Registers, for a particular range of interrupts, represent currently enabled interrupts. Non-present interrupts, depending on the Interrupt number field of the Interrupt Controller Type Register, related fields are read as zero and writing to these fields has no effect.

Interrupt Set-Pending Registers

These registers indicate the interrupts that are currently in pending state, bit read as 1, or to force some interrupts to enter pending state by overriding event detection on interrupt lines. Each set register is used for 32 interrupts therefore, the ARM1176 development chip uses two such registers.

Interrupt Set-Pending Register 0

Figure 3.37 shows the bit assignments for this register.

Figure 3.25. Interrupt Set-Pending Register 0 bit assignments

Table 3.26 lists the bit assignments for this register.

Table 3.26. Interrupt Set-Pending Register 0 bit assignments

Bits Offset Name Type Function

Bits	Offset	Name	Type	Function
[31:29]	`0x200`	Interrupt pending	RW	Writing 1 sets the interrupt pending bit and the corresponding interrupt enters pending state. Bit 31 is for the legacy nIRQ pin. Bit 30 is for private watchdog in an MPCore system and is not used in this SoC. Bit 29 is for private timer in an MPCore system and is not used in this SoC.
[28:16]	-	Interrupt pending	RO	Undefined interrupts, read as 0.
[15:0]	-	Interrupt pending	RO	Writing to IT0 to IT15 has not effect. Only the Software Interrupt Register can trigger these interrupts.

[31:29]

0x200

Interrupt pending

Writing 1 sets the interrupt pending bit and the corresponding interrupt enters pending state.

Bit 31 is for the legacy nIRQ pin.

Bit 30 is for private watchdog in an MPCore system and is not used in this SoC.

Bit 29 is for private timer in an MPCore system and is not used in this SoC.

[28:16]

Interrupt pending

Undefined interrupts, read as 0.

[15:0]

Interrupt pending

Writing to IT0 to IT15 has not effect. Only the Software Interrupt Register can trigger these interrupts.

Interrupt Set-Pending Register 1

Figure 3.26 shows the bit assignments for this register.

Figure 3.26. Interrupt Set-Pending Register 1 bit assignments

Table 3.27 lists the bit assignments for this register.

Table 3.27. Interrupt Set-Pending Register 1 bit assignments

Bits	Offset	Name	Type	Function
[31:0]	`0x204`	Interrupt pending	RW	Writing 1 sets the interrupt pending bit and the corresponding interrupt enters pending state

Note

You can only perform reads and writes by enabling the distributor through the distributor control register. described in Distributor Register Control Register.
For read status, you must set interrupt targets in the CPU targets registers, corresponding to hardware IRQs 32-63.

Writing a 1 to a bit through the Set-Pending Register means that the corresponding interrupt enters pending state. Writing a 1 sets the corresponding interrupt pending bit and a read reads back a 1. When set, you can only clear this bit using the Clear-Pending Register. Writing a 0 to the Set-Pending Register does not write a 0 to the corresponding interrupt pending bit.

Note

All RESERVED interrupts, spurious interrupts, and non-present interrupts, depending on the Interrupt Number field of the Interrupt Controller Type Register, and related fields are read as zero and writing to these fields has no effect.

The values read in the Set-Pending and Clear-Pending registers for the same interrupts range are the same. They both represent current pending interrupts. If a bit is read as 1, it implies that the interrupt is pending for at least one CPU.

Interrupt Clear-Pending Registers

These registers either determine that the registers that are currently in pending state and the bit is read as 1, or they force pending interrupts to return to the inactive state. Each set register is used for 32 interrupts. The ARM1176 Development Chip uses two such registers. The remaining ones are unused.

Interrupt Clear-Pending Register o

Figure 3.27 shows the bit assignments for this register.

Figure 3.27. Interrupt Clear-Pending Register 0 bit assignments

Table 3.28 lists the bit assignments for this register.

Table 3.28. Interrupt Clear-Pending Register 0 bit assignments

Bits Offset Name Type Function

[31:29]

Bits	Offset	Name	Type	Function
[31:29]	`0x280`	Interrupt pending	RW	Writing a 1 clears the interrupt enable bit and the corresponding interrupt enters pending state. A read returns a 0. Bit 31 is for the legacy nIRQ pin. Bit 30 is for private watchdog in an MPCore system and is not used in this SoC. Bit 29 is for private timer in an MPCore system and is not used in this SoC.
[28:16]	-	Interrupt pending	RO	Undefined interrupts, read as 0.
[15:0]	-	Interrupt pending	RO	Writing to bits corresponding to IT0 to IT15 has no effect. Only the Software Interrupt Register can trigger these interrupts.

0x280

Interrupt pending

Writing a 1 clears the interrupt enable bit and the corresponding interrupt enters pending state. A read returns a 0.

Bit 31 is for the legacy nIRQ pin.

Bit 30 is for private watchdog in an MPCore system and is not used in this SoC.

Bit 29 is for private timer in an MPCore system and is not used in this SoC.

[28:16]

Interrupt pending

Undefined interrupts, read as 0.

[15:0]

Interrupt pending

Writing to bits corresponding to IT0 to IT15 has no effect. Only the Software Interrupt Register can trigger these interrupts.

Interrupt Clear-Pending Register 1

Figure 3.28 shows the bit assignments for this register.

Figure 3.28. Interrupt Clear-Pending Register 1 bit assignments

Table 3.29 lists the bit assignments for this register.

Table 3.29. Interrupt Clear-Pending Register 1 bit assignments

Bits	Offset	Name	Type	Function
[31:0]	`0x284`	Interrupt pending	RW	Writing a 1 clears the interrupt enable bit and the corresponding interrupt enters pending state. A read returns a 0.

Writing a 1 clears the corresponding interrupt pending bit and a read reads back a 0. When cleared, you can only set this bit by using the Enable-Set Register. In other words, writing a 1 to the Enable-Clear Register does not write a 1 to the corresponding interrupt enable bit.

Note

All RESERVED interrupts, spurious interrupts, and non-present interrupts, depending on the Interrupt number field of the Interrupt Controller Type Register,and related fields are read as zero and writing to these fields has no effect.

The values read in the Pending-Set and Pending-Clear registers for the same interrupts range are the same, and represent current pending interrupts. If a bit is read as 1, it implies that the interrupt is pending.

Active Bit Registers

The Active Bit Register enables the software to find out the interrupts that are currently active, bit read as 1. They are read-only registers and writes to these registers are ignored. Because each register only handles 32 interrupts, there are two such registers in the chip. Figure 3.29 shows the bit assignments for these registers.

Figure 3.29. Active Bit Register 0 and 1 bit assignments

Table 3.30 lists the bit assignments for these registers.

Table 3.30. Active Bit Register 0 and 1 bit assignments

Bits Offset Name Type Function

[31:0]

Bits	Offset	Name	Type	Function
[31:0]	`0x300` `0x304`	Interrupt active bit	RO	Bit reads as 1: Corresponding interrupt is active Bit reads as 0: Corresponding interrupt is inactive

0x300 0x304

Interrupt active bit

Bit reads as 1: Corresponding interrupt is active

Bit reads as 0: Corresponding interrupt is inactive

Interrupt Priority Registers

These registers store the individual interrupt priority and16 levels of priority are supported.

Because each register sets the priority of four interrupts, there are 16 such registers in the ARM1176 Development Chip. You can set the priority for each interrupt by writing a value between 0x0-0xF to the corresponding bits for the interrupts in the registers described in this section. An interrupt with priority 0x0 has the highest priority, and an interrupt with priority 0xF is the lowest priority.

Note

You must never set the priority for an interrupt equal to the Priority Mask Register under normal operation. This is because the CPU interface does a strict comparison between the pending interrupt priority and the priority mask set in the Priority Mask Register. See Register summary. Because of this, if the priority mask is set to 0xF, interrupts of priority 0xF are not executed.

For interrupts with equal priority, the interrupt with the lowest ID is handled first, the interrupt with the second lowest ID is handled second, and the interrupt with the third lowest ID is handled third. If the two interrupts have the same ID, this can be the case for software interrupts, the lowest CPU source ID is executed first.

Interrupt Priority Register 0-3

Figure 3.30 shows the bit assignments for these registers.

Figure 3.30. Interrupt Priority Register 0-3 bit assignments

Table 3.31 lists the bit assignments for these registers.

Table 3.31. Interrupt Priority Register 0-3 bit assignments

Bits	Offset	Name	Type	Function
[31:28]	`0x400`	Priority N+3	RW	Interrupt priority
[27:24]	`0x404`	SBZ
[23:20]	`0x408`	Priority N+2
[19:16]	`0x40C`	SBZ
[15:12]	-	Priority N+1
[11:8]	-	SBZ
[7:4]	-	Priority N
[3:0]	-	SBZ

Interrupt Priority Register 4-6

Figure 3.31 shows the bit assignments for these registers.

Figure 3.31. Interrupt Priority Register 4-6 bit assignments

Table 3.32 lists the bit assignments for these registers.

Table 3.32. Interrupt Priority Register 4-6 bit assignments

Bits	Offset	Name	Type	Function
[31:28]	`0x410`	Priority N+3	RO	Interrupt priority
[27:24]	`0x414`	SBZ
[23:20]	`0x418`	Priority N+2
[19:16]	-	SBZ
[15:12]	-	Priority N+1
[11:8]	-	SBZ	RO	Interrupt priority
[7:4]	-	Priority N
[3:0]	-	SBZ

Interrupt Priority Register 7-15

Figure 3.32 shows the bit assignments for these registers.

Figure 3.32. Interrupt Priority Register 7-15 bit assignments

Table 3.33 lists the bit assignments for these registers.

Table 3.33. Interrupt Priority 7-15 Register bit assignments

Bits	Offset	Name	Type	Function
[31:28]	`0x41C`	Priority N+3	RW	Interrupt priority
[27:24]	`0x420`	SBZ
[23:20]	`0x424`	Priority N+2
[19:16]	`0x428`	SBZ
[15:12]	`0x42C`	Priority N+1
[11:8]	`0x430`	SBZ
[7:4]	`0x434`	Priority N
[3:0]	`0x438` `0x43C`	SBZ

Interrupt CPU Target Registers

These registers store the list of CPUs that each interrupt is sent to if the event defined by the Interrupt Controller Type Register occurs. Each bit in the Interrupt CPU Targets Register refers to one CPU. For the ARM1176JZF Development Chip, only one core is relevant. These registers are ignored in the case of software triggered interrupts.

This section describes the format of interrupt Interrupt CPU Targets Registers. Because each register is used for four interrupts, there are 16 registers in the development chip.

Interrupt CPU Target Registers 0-6

Figure 3.33 shows the bit assignments for these registers.

Figure 3.33. Interrupt CPU Target Registers 0-6 bit assignments

Table 3.34 lists the bit assignments for these registers.

Table 3.34. Interrupt CPU Target Registers 0-6 bit assignments

Bits	Offset	Name	Type	Function
[31:24]	`0x800`	CPU targets N+3^[1]	RO	Store list of CPUs that are sent interrupts
[23:16]	`0x804`	CPU targets N+2
[15:8]	`0x808`	CPU targets N+1
[7:0]	`0x80C` `0x810` `0x814` `0x818`	CPU targets N
^[1]Only one cpu is active and it is always CPU0.

Interrupt CPU Target Register 7

Figure 3.34 shows the bit assignments for this register.

Figure 3.34. Interrupt CPU Target Register 7 bit assignments

Table 3.35 lists the Interrupt CPU Target Register 7 bit assignments.

Table 3.35. Interrupt CPU Target Register 7 bit assignments

Bits	Offset	Name	Type	Function
[31:24]	`0x81C`	CPU targets N+3^[1]	RO	Store list of CPUs that are sent interrupts
[23:16]	-	CPU targets N+2
[15:8]	-	CPU targets N+1
[7:0]	-	CPU targets N
^[1]Only one cpu is active and it is always CPU0.

This register is for interrupts IT28, IT29, IT30, and IT31.

Note

For IT29, IT30 and IT31, values read in corresponding fields depend on the accessing CPU because these interrupt sources are private:

For CPU 0: CPU targets 29, 30 and 31 are read as 0x1. Writes are ignored.

In the particular implementation of the GIC in the ARM1176JZF Development Chip, there is only one CPU, CPU 0. The reset value of the CPU Target Register 8 is 0x01010100.

Interrupt CPU Target Register 8-15

Figure 3.35 shows the bit assignments for these registers.

Figure 3.35. Interrupt CPU Target Register 8-15

Table 3.36 lists the bit assignments for these registers. These bits correspond to a hardware interrupt. The reset value of these bits is 0.

Table 3.36. Interrupt CPU Target Register 8-15 bit assignments

Bits	Offset	Name	Type	Function
[31:28]	`0x820`	CPU targets N+3	RO^[1]	Store the list of CPUs that interrupts are sent to
[27:24]	`0x824`	CPU targets N+2
[23:20]	`0x828`	CPU targets N+1
[19:16]	`0x82C`	CPU targets N
[15:12]	`0x830`	-
[11:8]	`0x834`	-
[7:4]	`0x838`	-
[3:0]	`0x83C`	-
^[1]For bits assigned to registers 0x820 to 0x83c, only bits [0], [8], [16] and [24] are RW. The others are R0.

Interrupt Configuration Registers

Interrupt Configuration Registers define the interrupt line event that it is considered active and the software model. There can be up to 16 interrupt configuration registers.

Because each register handles only 16 interrupts, the ARM1176JZF Development Chip uses four such registers.

Note

IT 0 to 31 and 1 023 are special interrupts for each individual CPU:

IT0 to IT15 are defined as inter-processor interrupts
IT16 to IT28 are reserved
IT29 is defined as private timer interrupt
IT30 is defined as private watchdog interrupt, if in Timer mode
IT31 is defined as legacy nIRQ pin
IT1023 is defined as the spurious interrupt.

Corresponding fields are all read as 00 and write accesses to these fields are ignored for all interrupts except for the inter-processor interrupts, IT0 to IT15. You can configure IPI software models and apply them to the interrupts sent from the writing CPU.

These interrupts are aliased. An additional field in the Interrupt Acknowledge Register specifies the requesting processor.

Interrupt Configuration Register 0

Figure 3.36 shows the bit assignments for this register.

Figure 3.36. Interrupt Configuration Register 0 bit assignments

Table 3.37 lists the bit definition for this register.

Table 3.37. Interrupt Configuration Register 0 bit definition

Bits	Offset	Name	Type	Function
[31:30]	`0xC00`	ITn+15	RW	Configure software model for all 16 IPIs
[29:28]	-	ITn+14
[27:26]	-	ITn+13
[25:24]	-	ITn+12
[23:22]	-	ITn+11
[21:20]	-	ITn+10	RW	Configure software model for all 16 IPIs
[19:18]	-	ITn+9
[17:16]	-	ITn+8
[15:14]	-	ITn+7
[13:12]	-	ITn+6
[11:10]	-	ITn+5
[9:8]	-	ITn+4
[7:6]	-	ITn+3
[5:4]	-	ITn+2
[3:2]	-	ITn+1
[1:0]	-	ITn

Table 3.38 lists the Individual ITn encoding.

Table 3.38. Interrupt definition encoding

IT bit 0	Meaning
0	Interrupt line uses the N-NN software model
1	Interrupt line uses the 1-N software model
IT bit 1	Meaning
0	Interrupt line is considered as level HIGH active
1	Interrupt line is considered as rising edge sensitive

You can configure the software model of the interrupts applied to in this register, but not the edge and level configuration. The testmask of this register, for example, for PMAP testing, is 0x55555555.

Interrupt Configuration Register 1

Figure 3.37 shows the bit assignments for this register.

Figure 3.37. Interrupt Configuration Register 1 bit assignments

Table 3.39 lists the bit assignments for this register.

Table 3.39. Interrupt Configuration Register 1 bit assignments

Bits	Offset	Name	Type	Function
[31:30]	`0xC04`	ITn+15	RO	Configuration for IDs 16-28 and internal IRQs, 29, 30, and 31
[29:28]	-	ITn+14
[27:26]	-	ITn+13
[25:24]	-	ITn+12
[23:22]	-	ITn+11
[21:20]	-	ITn+10
[19:18]	-	ITn+9
[17:16]	-	ITn+8
[15:14]	-	ITn+7
[13:12]	-	ITn+6
[11:10]	-	ITn+5
[9:8]	-	ITn+4
[7:6]	-	ITn+3
[5:4]	-	ITn+2
[3:2]	-	ITn+1
[1:0]	-	ITn

This register is reserved for IDs 16-28 and internal IRQs, 29, 30, and 31. This register is read-only and you cannot configure it.

Interrupt Configuration Register 2-3

Figure 3.38 shows the bit assignments for these registers.

Figure 3.38. Interrupt Configuration Register 2-3 bit assignments

Table 3.40 lists the bit definition for these registers.

Table 3.40. Interrupt Configuration Register 2-3 bit definition

Bits	Offset	Name	Type	Function
[31:30]	`0xC08`	ITn+15	RW	Configure software model and edge and level for IDs 32-47, and 48-63
[29:28]	`0xC0C`	ITn+14
[27:26]	-	ITn+13
[25:24]	-	ITn+12
[23:22]	-	ITn+11
[21:20]	-	ITn+10
[19:18]	-	ITn+9
[17:16]	-	ITn+8
[15:14]	-	ITn+7
[13:12]	-	ITn+6
[11:10]	-	ITn+5
[9:8]	-	ITn+4
[7:6]	-	ITn+3	RW	Configure software model and edge and level for IDs 32-47, and 48-63
[5:4]	-	ITn+2
[3:2]	-	ITn+1
[1:0]	-	ITn

These two registers support hardware IRQs of ID 32-47, and 48-63. You can fully configure them.

Software Interrupt Register

The Software Interrupt Register is a write-only register that triggers an interrupt, identified by its own ID, to a list of CPUs. Figure 3.39 shows the bit assignments for this register.

Figure 3.39. Software Interrupt Register bit assignments

Table 3.41 lists the bit definition for this register.

Table 3.41. Software Interrupt Register bit definition

Bits	Offset	Name	Type	Function
[31:26]	`0xF00`	SBZ	WO	Trigger specific interrupt---
[25:24]	-	Target list filter^[1]
[23:16]	-	CPU target list^a
[15:10]	-	SBZ
[9:0]	-	Interrupt ID		Interrupt identifier
^[1]Allowed values that trigger an interrupt on CPU0 are: target list filter = 0x00 and bit [0] of CPU target set target list filter = 0x10.

The CPU target list can be different from the one defined in the CPU Target List Register for the specified interrupt ID.

The Target List filter definition is:

00: Interrupt sent to CPUs listed in CPU Target List
01: CPU target list is ignored, interrupt is sent to all but the requesting CPU
10: CPU target list is ignored, interrupt is sent to the requesting CPU only
11: Reserved.

Note

If you attempt to trigger an interrupt with an ID larger than the number of supported interrupts, or that references a CPU that is not present, there can be unpredictable effects in the interrupt distributor.

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