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The CPU interface registers are described in this section. Table 3.42 shows the CPU interface registers and the following sections provide details about each individual register.
Table 3.42. CPU interface registers
| Name | Offset | Type | Width | Reset | Description |
|---|---|---|---|---|---|
| Control | 0x000 | RW | 1 | 0x00000000 | Control register |
| PriorityMask | 0x004 | RW | 4 | 0x00000000 | Priority Mask register |
| BinaryPoint | 0x008 | RW | 3 | 0x00000003 | Binary Point register |
| IrqAck | 0x00C | RO | 13 | 0x000003FF | Interrupt Ack register |
| EndIrq | 0x010 | WO | 13 | - | End of Interrupt (EIO) register |
| RunningPriority | 0x014 | RO | 4 | 0x000000FF | Running Rriority register |
| HighestPendingIrq | 0x018 | RO | 13 | 0x000003FF | Highest Pending Interrupt register |
Table 3.43 shows bit assignments for the CPU Interface Control register.
Use the Priority Mask to prevent interrupts from being sent to the CPU. The CPU interface asserts an interrupt request to the CPU if, and only if, the priority of the highest pending interrupt sent by the interrupt distributor is strictly higher than the mask value set in the Priority Mask Register.
One consequence of the strict comparison is that lowest priority interrupt will never cause the assertion of interrupt request to the CPU. This allows an extra level of interrupt enabling. Although an interrupt can be pending, it will never be seen by the CPU. Table 3.44 shows bit assignments for the Priority Mask register.
Table 3.44. Priority Mask Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| Priority Mask | 7:4 | RW | Used to determine if the CPU interface asserts an interrupt request to CPU, if and only if the priority of the highest pending interrupt sent by the interrupt distributor is strictly higher than the mask set in this register. |
Binary point register is used to specify a certain number of bits to ignore in the priority comparison made in the CPU interface for pre-emption stack. Table 3.45 shows bit assignments for the Binary Pointer register.
Table 3.45. Binary Pointer Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| SBZ/UNP | 31:3 | RW | - |
| Binary Point | 2:0 | If this is set, ignore bits in priority comparison made in CPU interface for pre-emption stack. |
Table 3.46 shows the meanings for Binary Point values:
Table 3.46. Binary Point value meanings
| Value | Meaning |
|---|---|
| 000 | Bits [7:1] of the priority are used to determine pre-emption |
| 001 | Bits [7:2] of the priority are compared for pre-emption. |
| 010 | Bits [7:3] of the priority are compared for pre-emption. |
| 011 | Bits [7:4] of the priority are compared for pre-emption. |
| 100 | Bits [7:5] of the priority are compared for pre-emption. |
| 101 | Bits [7:6] of the priority are compared for pre-emption. |
| 110 | Bits [7:7] of the priority are compared for pre-emption. |
| 111 | No pre-emption is performed. All bits of the priority are used for prioritization. |
You can restrict the lowest value to any value from 0 to 4.
If you attempt to specify a value less than the set minimum, the
minimum value is used. This value can be read back to enable software
discovery. At reset, the register takes its minimum supported value.
The Interrupt Acknowledge Register is a read-only register used by the CPU to determine the ID of the interrupt asserted by the CPU interface. Table 3.47 shows bit assignments for the Interrupt Acknowledge Register.
Table 3.47. Interrupt Acknowledge Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| SBZ/RAZ | 31:13 | RO | - |
| CPU source ID | 12:10 | CPU source ID value. Depends on Interrupt ID field:
| |
| Interrupt ID | 9:0 | Interrupt identifier |
This write-only register is used when the software finishes handling an interrupt. Table 3.48 shows bit assignments for the EOI Register.
Table 3.48. End of Interrupt Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| SBZ/RAZ | 31:13 | WO | - |
| CPU source ID | 12:10 | CPU source ID value. Depends on Interrupt ID field:
| |
| Interrupt ID | 9:0 | Interrupt identifier |
This read-only register contains the priority level of the currently running interrupts on the CPU. Table 3.49 shows bit assignments for the Running Interrupt Register.
Table 3.49. Running interrupt Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| SBZ/UNP | 31:8 | RO | - |
| Priority | 7:4 | Indicates priority level of the current running interrupt. | |
| SBZ | 3:0 | - |
When no interrupt is running, defined as acknowledged by reading
acknowledge register but not ended by writing to EOI register, the
priority value read is 0xFF.
The Highest Pending Interrupt Register contains the Interrupt
ID and CPU ID of the Highest Pending Interrupt for this CPU. If
no interrupt is pending, the Interrupt ID returned is 0x3FF. This
indicates a spurious interrupt.
The format of the register is the same as the Interrupt Acknowledge Register. Table 3.50 shows bit assignments for the Highest Pending Interrupt Register.
Table 3.50. Highest Pending interrupt Register bit assignments
| Name | Bits | Type | Function |
|---|---|---|---|
| SBZ/RAZ | 31:13 | WO | - |
| CPU Source ID | 12:10 | CPU source ID value. Depends on Interrupt ID field:
| |
| Interrupt ID | 9:0 | Interrupt identifier |
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DDI 0375A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Generic Interrupt Controller (GIC) > CPU interface summary |