ARM1176JZF Development Chip Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the ARM1176JZF Development Chip
1.2. Component summary
1.2.1. CoreSight components
1.2.2. System components
1.2.3. TrustZone components
1.2.4. Intelligent Energy Manager (IEM) components
1.3. Technology summary
2. Functional Overview
2.1. About the ARM 1176JZF Development Chip
2.1.1. Processor subsystem
2.1.2. Level 2 Cache Controller
2.1.3. Intelligent Energy Management (IEM)
2.1.4. Voltage domains
2.1.5. AXI infrastructure
2.1.6. Clocking
2.1.7. Interrupt logic
2.1.8. Interrupt sources
2.1.9. On-chip RAM
2.1.10. Exclusive access
2.1.11. External static memory control
2.1.12. External dynamic memory control
2.2. System controller
2.2.1. Intelligent Energy Management (IEM)
2.2.2. Power modes
2.2.3. Remap controller
2.2.4. System reset controller
2.3. Intelligent Energy Management (IEM)
2.3.1. Dynamic Clock Generator (DCG)
2.3.2. Operation
2.3.3. Dynamic Voltage Scaling (DVS)
2.4. Generic Interrupt Controller (GIC)
2.5. CoreSight
2.5.1. AXI access
2.5.2. JTAG test access port
2.5.3. APB modification
2.5.4. ATB off-chip
2.5.5. Trigger connectivity
2.5.6. DapRomDefs file
2.6. Clock sources and domains
2.6.1. External clock sources
2.6.2. Internally generated clock sources
2.6.3. Exported clocks
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Memory maps
3.2.1. Boot and remap options
3.2.2. ARM1176JZF peripheral port memory map
3.2.3. ARM1176JZF DMA port, CLCDC, and CoreSight memory map
3.3. SoC configuration
3.3.1. Configuring the chip
3.3.2. Entering test mode
3.3.3. Controlling debug
3.3.4. Configuring security
3.3.5. Configuration block signals
3.4. Controlling the power modes
3.4.1. StandbyWFI mode
3.4.2. Dormant and shutdown mode
3.5. Configuring the IEC
3.5.1. Dynamic Clock Generator (DCG)
3.5.2. DCG fractional performance level mapping configuration
3.5.3. Dynamic Voltage Controller (DVC) index mapping
3.5.4. Processor frequency configuration
3.5.5. Dynamic Performance Monitor (DPM) frequency configuration
3.5.6. Target index and current index
3.6. System controller
3.6.1. Register summary
3.6.2. Register descriptions
3.7. Generic Interrupt Controller (GIC)
3.7.1. Register summary
3.7.2. Distributor Register descriptions
3.7.3. CPU interface summary
A. Electrical and Physical Characteristics
A.1. About electrical and physical characteristics
A.2. Electrical requirements
A.3. Bonding and pinout
A.3.1. Pad types
A.3.2. Die bonding
A.4. Physical characteristics
A.4.1. Flipchip package
A.4.2. Process
A.4.3. Bumping
A.4.4. Package marking
A.4.5. IO pad ring design
A.4.6. Power and ground sources
B. Component Revision Status
B.1. Components
B.2. Third party components
B.3. IP modifications
B.4. Custom IP
B.5. Configured IP
Glossary

List of Figures

1. Key to timing diagram conventions
2.1. ARM1176JZF Development Chip block diagram
2.2. IEM subsystem
2.3. CoreSight subsystem
2.4. APB peripherals
2.5. Secure and non-secure interrupt structure
2.6. SMC AXI interface logic
2.7. user_config Register bit assignment
2.8. user_status Register bit assignment
2.9. System controller top-level
2.10. IEM performance level and PLL controller
2.11. Performance decrease to running on PLL1 from PLL2
2.12. Performance decrease to running on PLL2 from PLL1
2.13. Performance increase to running on PLL2 from PLL1
2.14. Performance increase to running on PLL1 from PLL2
2.15. Increase to maximum performance
2.16. Remap logic
2.17. IEM block diagram
2.18. DCG block diagram part 1
2.19. DCG block diagram part 2
2.20. PLL block
2.21. Clock divider block diagram
2.22. Clock divide circuit
2.23. Example divide by 4
2.24. ETM and L2CC StandbyWFI clock gate
2.25. Switching with performance requirement optimization
2.26. Switching without performance requirement optimization
2.27. Standard APCI closed loop behavior
2.28. Improved closed loop with target voltage under DCG control
2.29. Clock enable control between synchronous and asynchronous modes
2.30. DVS emulation example
2.31. CoreSight architecture
2.32. CoreSight trigger connectivity
3.1. ARM 1176JZF peripheral port memory map
3.2. ARM 1176JZF DMA port, CLCDC, and CoreSight memory map
3.3. Configuration capture sequence
3.4. TZPCDECPROT0 Register bit assignments
3.5. TZPCDECPROT1 Register bit assignments
3.6. TZPCDECPROT2 Register bit assignments
3.7. DCG block diagram part 1
3.8. DCG block diagram part 2
3.9. CoreID Register bit assignments
3.10. SoCConfig1 Register bit assignments
3.11. SocConfig2 Register bit assignments
3.12. System Control Register bit assignments
3.13. System Status Register bit assignments
3.14. DCGIDXMAP registers to IECCFGDCGIDXMAP configuration inputs
3.15. DCGPERFMAP registers to IECCFGDCGPERFMAP configuration inputs
3.16. PLL Configuration Settings Register bit assignments
3.17. SMC Exclusive Access Monitor ID Register bit assignments
3.18. DLL Calibrate Register
3.19. Distributor Register Control Register bit assignments
3.20. Interrupt Controller Type Register bit assignments
3.21. Interrupt Set-Enable Register 0 bit assignments
3.22. Interrupt Set-Enable Register 1 bit assignments
3.23. Interrupt Clear-Enable Register 0 bit assignments
3.24. Interrupt Clear-Enable Register 1 bit assignments
3.25. Interrupt Set-Pending Register 0 bit assignments
3.26. Interrupt Set-Pending Register 1 bit assignments
3.27. Interrupt Clear-Pending Register 0 bit assignments
3.28. Interrupt Clear-Pending Register 1 bit assignments
3.29. Active Bit Register 0 and 1 bit assignments
3.30. Interrupt Priority Register 0-3 bit assignments
3.31. Interrupt Priority Register 4-6 bit assignments
3.32. Interrupt Priority Register 7-15 bit assignments
3.33. Interrupt CPU Target Registers 0-6 bit assignments
3.34. Interrupt CPU Target Register 7 bit assignments
3.35. Interrupt CPU Target Register 8-15
3.36. Interrupt Configuration Register 0 bit assignments
3.37. Interrupt Configuration Register 1 bit assignments
3.38. Interrupt Configuration Register 2-3 bit assignments
3.39. Software Interrupt Register bit assignments
A.1. Flipchip CABGA package cross-section
A.2. Example package markings

List of Tables

2.1. L2C master port transactions
2.2. 64-bit AXI infrastructure arbitration priority
2.3. 64-bit AXI make-up
2.4. ID merge function
2.5. DMC QoS options
2.6. 32-bit AXI ID make-up
2.7. Interrupt source allocation
2.8. user_config Register functionality in PL340
2.9. user_status Register functionality in PL340
2.10. IEC Maxperf and wake-up sources
2.11. System clock divide ratio options
2.12. Example system frequencies with 320MHz CPU speed
2.13. DCG resets
2.14. Asynchronous resets
2.15. SoC reset signals
2.16. JTAG TAP selection
2.17. CTI #0 connectivity
2.18. CTI #1 connectivity
2.19. External clock sources
2.20. Internally generated clock sources
2.21. Exported clocks
3.1. Remap options
3.2. Test mode configuration inputs
3.3. TZPCDECPROT0 Register bit assignments
3.4. TZPCDECPROT1 Register bit assignments
3.5. TZPCDECPROT2 Register bit assignments
3.6. AXI slave port security override
3.7. Configuration block signals
3.8. IEC performance levels
3.9. System controller register summary
3.10. CoreID Register bit assignments
3.11. SoCConfig1 Register bit assignments
3.12. SoCConfig2 Register bit assignments
3.13. System Control Register bit assignments
3.14. System Status Register bit assignments
3.15. PLL Configuration Settings Registers bit assignments
3.16. 64-bit AXI Priority Register bit assignments
3.17. SMC Exclusive Access Monitor ID Register bit assignments
3.18. DLL Calibrate Outputs Register bit assignments
3.19. Distributor Register summary
3.20. Distributor Register Control Register bit assignments
3.21. Interrupt Controller Type Register bit assignments
3.22. Interrupt Set-Enable Register 0 bit assignments
3.23. Interrupt Set-Enable Register 1 bit assignments
3.24. Interrupt Clear-Enable Register 0 bit assignments
3.25. Interrupt Clear-Enable Register 1 bit assignments
3.26. Interrupt Set-Pending Register 0 bit assignments
3.27. Interrupt Set-Pending Register 1 bit assignments
3.28. Interrupt Clear-Pending Register 0 bit assignments
3.29. Interrupt Clear-Pending Register 1 bit assignments
3.30. Active Bit Register 0 and 1 bit assignments
3.31. Interrupt Priority Register 0-3 bit assignments
3.32. Interrupt Priority Register 4-6 bit assignments
3.33. Interrupt Priority 7-15 Register bit assignments
3.34. Interrupt CPU Target Registers 0-6 bit assignments
3.35. Interrupt CPU Target Register 7 bit assignments
3.36. Interrupt CPU Target Register 8-15 bit assignments
3.37. Interrupt Configuration Register 0 bit definition
3.38. Interrupt definition encoding
3.39. Interrupt Configuration Register 1 bit assignments
3.40. Interrupt Configuration Register 2-3 bit definition
3.41. Software Interrupt Register bit definition
3.42. CPU interface registers
3.43. CPU Interface Control register bit assignments
3.44. Priority Mask Register bit assignments
3.45. Binary Pointer Register bit assignments
3.46. Binary Point value meanings
3.47. Interrupt Acknowledge Register bit assignments
3.48. End of Interrupt Register bit assignments
3.49. Running interrupt Register bit assignments
3.50. Highest Pending interrupt Register bit assignments
A.1. Pad type
A.2. Die bonding
A.3. I/O cell usage for inline design
B.1. Product revisions
B.2. Third party IP revisions
B.3. IP modifications
B.4. Custom IP descriptions

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A31 August 2007First release of r0p0.
Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0375A
Non-Confidential