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This write-only register is the holding register for the opmode<x>_<n> working registers. You cannot write to it in either the Reset or low-power states. Figure 3.12 shows the register bit assignments.
Table 3.8 describes register holding, see Memory manager operation for more information.
Table 3.8 lists the register bit assignments.
Table 3.8. set_opmode Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:16] | - | Reserved, undefined, write as zero. |
| [15:13] | set_burst_align | Holding register for value to be written to the specific SRAM chip opmode Register burst_align field. When you configure the controller to perform synchronous transfers[1], these bits determine whether memory bursts are split on memory burst boundaries: b000 = bursts can cross any address boundary b001 = burst split on memory burst boundary, that is, 32 beats for continuous b010 = burst split on 64 beat boundary b011 = burst split on 128 beat boundary b100 = burst split on 256 beat boundary b101 - b111 = reserved. For a NAND memory interface these bits are reserved, and written as zero. |
| [12] | set_bls | Holding register for value to be written to the specific SRAM chip opmode Register byte lane strobe (bls) field. This bit affects the assertion of the byte-lane strobe outputs. 0 = bls timing equals chip select timing. This is the default setting. 1 = bls timing equals we_n timing. This setting is used for eight memories that have no bls_n inputs. In this case, the bls_n output of the memory controller is connected to the we_n memory input. For a NAND memory interface this bit is reserved, and written as zero. |
| [11] | set_adv | Holding register for value to be written to the specific SRAM chip opmode Register address valid (adv) field. The memory uses the address advance signal adv_n when set. For a NAND memory interface this bit is reserved, and written as zero. |
| [10] | set_baa | Holding register for value to be written to the specific SRAM chip opmode Register burst address advance (baa) field. The memory uses the baa_n signal when set. For a NAND memory interface this bit is reserved, and written as zero. |
| [9:7] | set_wr_bl | Holding register for value to be written to the specific SRAM chip opmode Register bls field. Encodes the memory burst length: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous b110 - b111 = reserved. For a NAND memory interface these bits are reserved, and written as zero. |
| [6] | set_wr_sync | Holding register for value to be written to the specific SRAM chip opmode Register wr_sync field. The memory writes are synchronous when set. For a NAND memory interface this bit is reserved, and written as zero. |
| [5:3] | set_rd_bl | Holding register for value to be written to the specific SRAM chip opmode Register bls field. Encodes the memory burst length: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous b110 - b111 = reserved. For a NAND memory interface these bits are reserved, and written as zero. |
| [2] | set_rd_sync | Holding register before being written to the specific SRAM chip opmode Register rd_sync field. Memory in sync mode when set. For a NAND memory interface this bit is reserved, and written as zero. |
| [1:0] | set_mw | Holding register for value to be written to the specific SRAM chip opmode Register memory width (mw) field. Encodes the memory data bus width: b00 = 8 bits[2] b01 = 16 bits[2] b10 = 32 bits b11 = reserved. You can program this to the configured width, or half that width. See Memory Interface Configuration Register. |
[1] For asynchronous transfers:
[2] For a NAND interface, only 8-bit and 16-bit are valid settings. | ||
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380F |
| Non-Confidential | |
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