3.3.6. set_cycles Register
This write-only register is the holding register for the sram<n>_cycles
and nand<n>_cycles Registers. This register enables you to set
the time interval for holding registers before writing to certain
memory manager specific registers. You cannot write to this register
in either the Reset or low-power states. Figure 3.11 shows the register bit assignments.
Table 3.7 lists
the register bit assignments.
Table 3.7. set_cycles Register bit assignments
| Bits | Name | Function |
|---|
| [31:23] | - | Reserved, undefined, write as zero |
| [22:20] | Set_t6 | Holding register for value to be written to
the specific NAND chip Register tRR field |
| [19:17] | Set_t5 | Holding register for value to be written to
the specific chip Register tTR or tAR fields |
| [16:14] | Set_t4 | Holding register for value to be written to
the specific chip Register tPC or tCLR fields |
| [13:11] | Set_t3 | Holding register for value to be written to
the specific chip Register tWP field |
| [10:8] | Set_t2 | Holding register for value to be written to
the specific chip Register tCEOE or tREA fields |
| [7:4] | Set_t1 | Holding register for value to be written to
the specific chip Register tWC field |
| [3:0] | Set_t0 | Holding register for value to be written to
the specific chip Register tRC field |
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