PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual 3.3.10. sram

3.3.10. sram_cycles Register

There is an instance of this register for each SRAM chip supported. You cannot read the read-only sram_cycles Register in the Reset state. Figure 3.15 shows the register bit assignments.

Figure 3.15. sram_cycles Register bit assignments

Table 3.11 lists the register bit assignments.

Table 3.11. sram_cycles Register bit assignments

Bits	Name	Function
[31:20]	-	Reserved, read undefined.
[19:17]	t_tr	Turnaround time for SRAM chip configurations. Minimum permitted value = 1.
[16:14]	t_pc	Page cycle time for SRAM chip configurations. Minimum permitted value = 1.
[13:11]	t_wp	we_n assertion delay. Minimum permitted value = 1.
[10:8]	t_ceoe	oe_n assertion delay for SRAM chip configurations. Minimum permitted value = 1.
[7:4]	t_wc	Write cycle time. Minimum permitted value = 2.
[3:0]	t_rc	Read cycle time. Minimum permitted value = 2.

Copyright © 2005-2007 ARM Limited. All rights reserved.	ARM DDI 0380F
Non-Confidential
PDF version