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The memory interface issues commands to the memory from the command FIFO, and controls the cycle timings of these commands. It only issues a new command after the previous command is complete and any turn-around times have been met. It only issues a read command when there is space for all the impending data in the read data FIFO.
The rd_bl parameter
in the opmode Register must not be set greater than the read data
FIFO depth.
The controller does not perform WRAP transfers on the memory interface. For memory devices that only operate in WRAP mode, you must align transfers to a memory burst boundary. If the controller performs transfers that cross a memory boundary, then you must program the memory device to operate in INCR mode.
If enabled, the EBI can prevent commands being issued when the SMC is not granted the external bus.
Figure 2.13 to Figure 2.24 show the timing parameters. They are divided into the following:
The internal signal read_data is included in the read transfer waveforms to indicate the clock edge on which data is registered by the SMC.
All address, control, and write data outputs of the SMC are registered on the rising edge of mclk<x>n, equivalent to the falling edge of mclk<x>, for both synchronous and asynchronous accesses. The clock output to memory, clk_out, is driven directly by mclk<x>, but gated to prevent toggling during asynchronous accesses, or when no transfers are occurring.
Read data output by the memory device is also registered on the rising edge of mclk<x>n, equivalent to the falling edge of mclk<x>, for asynchronous reads. For synchronous reads, read data is registered using the fed-back clock, fbclk_in. For synchronous and asynchronous accesses, the data is then pushed onto the read data FIFO to be returned by the AXI interface.
This subsection describes:
Table 2.3 and Table 2.4 list the opmode<x>_<n> and sram_cycles Register settings. See Table 3.1.
Where:
x = 0 or 1, for interface 0 and 1
n = 0 to 3, for chip select.
Table 2.3. Asynchronous read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 0 | 3’b000 | - | - | - | - | - | - |
Table 2.4. Asynchronous read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0011 | - | 3’b001 | - | - | - |
Figure 2.13 shows a single asynchronous read transfer with an initial access time, tRC, of 3 cycles and an output enable assertion delay, tCEOE, of one cycle.
Table 2.5 and Table 2.6 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.5. Asynchronous read in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 0 | 3’b000 | - | - | - | 1 | - | - |
Table 2.6. Asynchronous read in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0111 | - | 3’b101 | - | - | - |
Figure 2.14 shows a single asynchronous read transfer in multiplexed SRAM mode, with tRC = 7, and tCEOE = 5.
In multiplexed mode, both address and data are output by the SMC on the data_out output bus. Read data is accepted on the data_in bus. The address is still driven onto the address bus in multiplexed mode. This enables you to use the upper address bits for memories that require more address bits than data bits.
Table 2.7 and Table 2.8 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.7. Asynchronous write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | - | - | 0 | 3’b000 | - | - | - | - |
Table 2.8. Asynchronous write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | - | 4’b0100 | - | 3’b010 | - | - |
Figure 2.15 shows an asynchronous write with a write cycle time tWC of four cycles and a we_n assertion duration, tWP, of two cycles.
The timing parameter tWP controls the deassertion of we_n. You can use it to vary the hold time of cs_n, addr and data. This differs from the read case where the timing parameter tCEOE controls the delay in the assertion of oe_n. Additionally, we_n is always asserted one cycle after cs_n to ensure the address bus is valid.
Table 2.9 and Table 2.10 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.9. Asynchronous write in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | - | - | 0 | 3’b000 | 0 | 0 | - | - |
Table 2.10. Asynchronous write in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | - | 4’b0111 | - | 3’b100 | - | - |
Figure 2.16 shows an asynchronous write in multiplexed mode. tWC is seven cycles, and tWP is four cycles.
For writes in multiplexed mode, you must set tWC ≥ tWP + 2. The constant value of two represents the two mclk cycles of the address phase.
Table 2.11 and Table 2.12 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.11. Page read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 0 | <page length> | - | - | - | - | - | 1 |
Table 2.12. Page read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0011 | - | 3’b010 | - | 3’b001 | - |
Figure 2.17 shows a page read access, with an initial access time, tRC, of three cycles, an output enable assertion delay, tCEOE, of two cycles, and a page access time, tPC, of one cycle.
You enable Page mode in the SMC by setting the opmode Register for the relevant chip to asynchronous reads, and the burst length to the page size.
Multiplexed mode page accesses are not supported.
Table 2.13 and Table 2.14 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.13. Synchronous burst read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 1 | <burst length> | - | - | - | 1 | - | - |
Table 2.14. Synchronous burst read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0100 | - | 3’b010 | - | - | - |
Figure 2.18 shows a burst read with the wait output of the memory used to delay the transfer.
Synchronous memories have a configuration register enabling wait to be asserted either on the same clock cycle as the delayed data, or a cycle early. The SMC only supports wait being asserted one cycle early, enabling wait to be initially sampled with the fed-back clock and then with mclk before being used by the FSM. This enables the easiest timing closure. Additionally, you must configure the memory for wait to be active LOW.
In synchronous operation, the SMC relies on the wait signal being de-asserted HIGH to indicate that the memory can finish the transfer. When in synchronous mode, some memories do not de-assert the wait signal during non-array read transfers. Non-array read transfers are typically status register reads. To avoid stalling the system with these memories, in synchronous mode you must not perform non-array read transfers with the memory and SMC.
You must set tRC to a value that enables wait_reg_mclk to stabilize. See Figure 2.18.
Table 2.15 and Table 2.16 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.15. Synchronous burst read in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 1 | <burst length> | - | - | - | - | - | - |
Table 2.16. Synchronous burst read in multiplexed mode read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0100 | - | 3’b010 | - | - | - |
Figure 2.19 shows the same synchronous read burst transfer as Figure 2.18, but in multiplexed mode.
Table 2.17 and Table 2.18 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.17. Synchronous burst write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | - | - | 1 | <burst length> | - | 1 | - | - |
Table 2.18. Synchronous burst write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | - | 4’b0100 | - | 3’b001 | - | - |
Figure 2.20 shows a synchronous burst write transfer that is delayed by the wait signal. You must configure the memory to assert wait one cycle early and with an active LOW priority. The wait signal is again registered with the fed-back clock and mclk before being used. The wait signal is used in the mclk domain to the memory interface FSM.
Synchronous memories have a configuration register enabling wait to be asserted either on the same clock cycle as the delayed data, or a cycle early. The SMC only supports wait being asserted one cycle early, enabling wait to be initially sampled with the fed-back clock and then with mclk before being used by the FSM. This enables the easiest timing closure. Additionally, you must configure the memory for wait to be active LOW.
You must set tWC to a value that enables wait_reg_mclk to stabilize. See Figure 2.20.
Table 2.19 and Table 2.20 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.19. Synchronous burst write in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | - | - | 1 | <burst length> | - | 1 | - | - |
Table 2.20. Synchronous burst write in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | - | 4’b0100 | - | 3’b001 | - | - |
Figure 2.21 shows the same synchronous burst write as Figure 2.20, but in multiplexed mode.
Table 2.21 and Table 2.22 list the opmode<x>_<n> and sram_cycles Register settings.
Table 2.21. Synchronous read and asynchronous write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
| Value | - | 1 | 3’b001 | 0 | 3’b000 | 0 | 1 | 0 | - |
Table 2.22. Synchronous read and asynchronous write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
| Value | 4’b0100 | 4’b0110 | 3’b010 | 3’b001 | - | 3’b011 |
Figure 2.22 shows the turnaround time tTR, enforced between synchronous read and asynchronous write. The turnaround time is enforced between:
reads followed by writes
writes followed by reads
read following a read from a different chip select.
For tRC:
when using memory devices that are not wait-enabled, you must program tRC to be the number of clock cycles required before valid data is available following the assertion of cs_n
when using memory devices that are wait-enabled, you must program tRC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:
t_RC = 3 + t_CEOE
t_CEOE is only required if wait is asserted when oe_n goes LOW.
For tWC:
when using memory devices that are not wait-enabled, you must program tWC to be the number of clock cycles required before the first data is written, following the assertion of cs_n
when using memory devices that are wait-enabled, you must program tWC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:
t_WC = 3
If a memory device is configured so that there are two or less clock cycles between the assertion of wait and data being required then you must program tWC as if the memory device is not wait-enabled.
During repeated access to the same chip, the SMC can keep chip select asserted. To support memories that require chip select to be deasserted periodically, you can program the refresh_period_<x> Register to set a maximum number of consecutive memory bursts. You can set the number of consecutive bursts from one to 15, inclusive. See refresh_period_0 Register and refresh_period_1 Register.
All NAND control and data outputs are registered on the falling edge of mclk. Additionally, read data from the memory device is registered by the SMC on the falling edge of mclk before being pushed onto the read data FIFO.
NAND opmode registers only set memory width and are not included in this section.
The following apply to NAND accesses:
When doing a command with address cycles = 0, always enable at least one byte lane.
Read data phases cannot have end commands associated with them.
This section describes:
Table 2.23 lists the nand_cycles Register settings.
Table 2.23. NAND flash address input nand_cycles Register settings
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_rr |
| Value | - | 4’b0010 | - | 3’b001 | - | - | - |
Figure 2.23 shows an address input phase. The cycle time is set to two, and the we_n assertion duration set to one. The address consists of three cycles, and the second command is also required.
Table 2.24 lists example awaddr fields for NAND flash address input.
Table 2.25 lists the nand_cycles Register settings.
Table 2.25. NAND flash read nand_cycles Register settings
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_rr |
| Value | 4’b0011 | - | 3’b010 | - | - | - | - |
Figure 2.24 shows a read from NAND flash. The cycle time is set to three and the re_n assertion delay to two cycles. Three data items are read.
Table 2.26 lists example araddr fields for NAND flash page read.
Table 2.27 lists the address latch to data phase Register settings.
Table 2.27. Address latch to data phase Register settings
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_rr |
| Value | 4’b0011 | 4'b0010 | 3’b010 | 3'b001 | - | 3'b010 | - |
Figure 2.25 shows
tAR that is the number of extra cycles delay
between Address latch (ale) falling
and the start of a new data_phase command.
Table 2.28 lists the busy synchronization to data phase Register settings.
Table 2.28. Busy synchronization to data phase Register settings
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_rr |
| Value | 4’b0011 | - | 3’b010 | - | - | = | 3'b010 |
Figure 2.26 shows
tRR that is the number of extra cycles delay
between the synchronization of the busy signal
and the start of the next data_phase command.
It is is only used when nand_boot_en is
asserted.
Table 2.29 lists the command latched to data phase Register settings.
Table 2.29. Command latched to data phase Register settings
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_rr |
| Value | 4’b0011 | 4'b0010 | 3’b010 | - | 3'b010 | = | - |
Figure 2.27 shows
the tCLR delay that is the number of extra
cycles delay between a command being latched, cle HIGH,
and the start, CS asserted, of
a data_phase command.
The tCLR delay is applied before both read and write data phase commands.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380F |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Functional operation > Memory interface operation |