PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual 2.2.9. Error Correction Code operation

2.2.9. Error Correction Code operation

An ECC block can be included for each NAND interface at the configuration stage. It operates on a number of 512 byte blocks of NAND memory and can be programmed to store the ECC codes after the data in memory. For writes, the ECC is written to the spare area of the page. For reads, the result of a block ECC check are made available to the device driver.

Note

Because there is a no standard interface for NAND memory devices, it is important to know the characteristics of a particular memory type, before you enable ECC functionality within the SMC.

A configuration option enables an extra block of 4, 8, 16 or 32 bytes to be included at the end of the page, before the start of the ECC codes. Figure 2.28 shows the ECC block structure in memory.

Figure 2.28. ECC block structure

Operation

The ECC calculation uses a simple Hamming code, using 1 bit correction 2 bit detection. It starts when a valid read or write command with a 512 byte aligned address is detected on the memory interface, and the block is enabled using the ecc_memcfg register. Values stored in the ecc_memcommand<x> registers are used to detect the start of an address phase access.

Figure 2.29 gives an overview of how the ECC operates.

Figure 2.29. ECC state diagram

A 24-bit ECC code is generated for each 512 byte block and a shorter code between 10 and 16 bits for the extra block.

Note

For a 16-bit interface, ECC codes are written to memory aligned to 16-bit boundaries.

Figure 2.30 shows the basic operation with no reading ECC values between blocks.

Figure 2.30. Basic operation

Addressing

The ECC block supports two addressing modes. This must be set correctly for the type of memory in use, because it is used when generating addresses to move around the NAND page, and for detecting 512 byte aligned addresses.

Normal mode addressing

The normal mode, setting ecc_ignore_add_eight = 0, expects the first two bytes to contain just the column address bits as Table 2.30 shows.

Table 2.30. Normal mode addressing

Cycle	I/O 7	I/O 6	I/O 5	I/O 4	I/O 3	I/O 2	I/O 1	I/O 0
1st	A7	A6	A5	A4	A3	A2	A1	A0
2nd	L^[1]	L^[1]	L^[1]	L^[1]	A11^[2]/L	A10	A9	A8
3rd-7th	DC	DC	DC	DC	DC	DC	DC	DC
^[1]These bits must be Low otherwise the behavior is undefined. ^[2]A11 might be present, depending on the memory width.

DC = Don't care L = LOW

This mode supports all random access, column change commands, and up to four 512 blocks. See Address jumping.

Secondary mode addressing

The second mode, setting ecc_ignore_add_eight = 1, supports memories with 512 bits where the address formatting is as Table 2.31 lists.

Table 2.31. Second mode addressing

Cycle	I/O 7	I/O 6	I/O 5	I/O 4	I/O 3	I/O 2	I/O 1	I/O 0
1st	A7	A6	A5	A4	A3	A2	A1	A0
2nd	DC	DC	DC	DC	DC	DC	DC	DC
3rd-7th	DC	DC	DC	DC	DC	DC	DC	DC

DC = Don't care

Note

In this mode, A8 is passed as part of the start command and is not present in the data.

In this mode, random accesses are not possible. The nand_rd_col_change bits in the ecc_memcommand2 register can be used as an alternative read start command. This enables ECC calculation on just the extra block at the end of the page.

For writes, issuing a zero address cycle, pointer change command, that matches the nand_rd_col_change command, tells the ECC block that the next write command is to the extra bits. This only applies to the subsequent write command, even if the memory only requires one pointer access for multiple writes.

Data

When a valid start address has been sent, data can be read or written using a series of NAND data phase commands. See NAND data phase transfers. The last access must align with the end of a 512 byte block, or the extra block if it is enabled. You must set ECC Last on the last data phase access, to tell the ECC block not to expect any more data.

If an access to a different chip, is received during an ECC operation, the ECC block aborts and issues a Data stop after incomplete block error in the ecc_status register. No more ECC codes are read or written to memory.

Address jumping

To enable you to write individual 512 byte blocks, or the ECC extra block, the controller can issue address phase commands to move around the NAND page.

The ecc_jump setting in the status register controls how the controller jumps to the correct place in memory. It can be programmed to jump using full NAND commands, column change (random access) commands, or not to jump at all.

When using full NAND commands, the commands stored in ecc_memcommand1 are used to control the NAND address pointer. They are also used to detect the start of a NAND read or write. When the ECC block is set to jump, using column change commands, the commands stored in ecc_memcommand2 are used. The value used as the end command for a write access is taken directly from the previous AXI command that had the end_command_valid bit asserted.

The ECC values for writes are only written to memory after the end command is received. For reads, the ecc_read_end setting can be used to read ECC codes from memory between every block.

Address modes

This section describes the different methods used to control the address pointer, when writing ECC codes. The same methods can be applied to reads, except that end commands may be output after the address, if enabled in the ecc_memcommand<x> registers, but never after a data transfer.

ecc_jump = no jumping

If ecc_jump is set to no jumping, and not all blocks in a page are read or written, then an error is generated. However, the calculated ECC codes are available using the APB interface. If required, you can then use software to write them to memory. See Figure 2.31.

Figure 2.31. Every block is written

Note

The command values shown in these diagrams, for example 80, 10, or 15, are representative and may not match your particular NAND device.

ecc_jump = column change

If ecc_jump is set to column change commands, the controller issues a col_change command, with two address cycles. See Figure 2.32.

Figure 2.32. Not every block written, random access

ecc_jump = full command

If a full command is used, the controller issues an entire new command phase access with the same number of address cycles as the initial write. See Figure 2.33.

Figure 2.33. Full jumping

Note

If ecc_jump is set to use full commands, this counts against the maximum number of program operations before a NAND page must be erased.
If ecc_read_end is set to read between blocks, then each boundary must be aligned with the end of a data phase access. Otherwise, data phases accesses can cross boundaries between blocks.

ignore_add_8 and ecc_jump is not no_jump

If not all blocks are written, the controller issues a pointer change command using the value in the nand_rd_col_change bits of the mem_command register. For reads, the nand_rd_col_change bits are used instead of the standard read command, to access the extra bits at the end of the page. See Figure 2.34.

Figure 2.34. addressing mode ignore_add_8 with extra blocks

Note

After writing or reading ECC values in the secondary addressing mode, see Secondary mode addressing, the ECC block does not return the pointer to its previous state. Software might have to correct the pointer, depending on the memory and if the ECC block was forced to jump into the extra data area.

Cache mode accesses

If performing cache mode reads, the entire page must be read and ECC Last only issued on the last data_phase access of the last page. Undefined behavior occurs if you attempt to read data beyond the page size.

Note

ecc_jump must be set to no jump to prevent the controller from attempting to move the address pointer around the cache register.
If multiple pages are read, it is the job of software to maintain a count of the number of pages. All block valid and read flags are cleared when the first block of a new page is read.

Error Codes

The error code available from the ecc_status register applies to the previous ECC operation. It must only be considered valid when the ECC block is not busy.

Interrupts

Interrupts can be generated:

when the ECC block detects an error on a read
when an ECC code is read from memory, if the ecc_int_read bit is set
when an error occurs, if the ecc_int_abort bit is set.

Interrupts can be cleared by:

writing to the interrupt flag in the ecc_status register

writing any value to the block register.

Note

To enable the external interrupt, the ecc_intx_en bit must be set using the memc_cfg_set register in PL35x.

Correcting errors

If an error occurs, ecc_fail for that block is set. If the error is correctable, then the ecc_correct flag is set and the ecc_value gives the location of the bit that must be corrected.

The bottom three bits give the bit number, and the remaining bits form the byte number. For example, an ecc_value of 0x101 implies bit 1 of byte 32 is incorrect.

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