PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual 3.3.15. ECC Status Register

3.3.15. ECC Status Register

The ecc_status Register is read-only and contains status information for the ECC.

Although this is a read-only register, the bottom five bits can be written to clear the corresponding interrupts. Figure 3.20 shows the register bit assignments.

Figure 3.20. ecc_status Register bit assignments

Table 3.16 lists the register bit assignments.

Table 3.16. ecc_status Register bit assignments

Bits	Name	Function
[31:29]	-	Reserved, read undefined.
[29:25]	ecc_read	Read flags for ECC blocks. Indicates whether the stored ECC value for each block has been read from memory 0 = not read 1 = read.
[24:20]	ecc_can_correct	Correctable flag for each ECC block. Indicates if the detected error is correctable. 0 = not correctable 1 = correctable.
[19:15]	ecc_fail	Pass/fail flag for each ECC block.
[14:10]	ecc_value_valid	Valid flag for each ECC block.
[9]	ecc_read_not_write	0 = write 1 = read.
[8:7]	ecc_last_status	b00 = Completed successfully b01 = Unaligned Address, or out-of-range b10 = Data stop after incomplete block b11 = Data stopped but values not read/written because of ecc_jump value. Note The ecc_last_status bit is only updated at the completion of an ECC calculation.
[6]	ecc_status	Describes the status of the ECC block 0 = idle 1 = busy.
[5] [4] [3] [2] [1] [0]	raw_int_status	The interrupts ^[1] are: Abort. Extra block (if used). Block 3. Block 2. Block 1. Block 0.
^[1]To clear the interrupt, you must write a 1 to the appropriate bit.

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3.3.15. ECC Status Register

Note