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All address, control, and write data outputs of the SMC are registered on the rising edge of mclk<x>n, equivalent to the falling edge of mclk<x>, for both synchronous and asynchronous accesses. The clock output to memory, clk_out, is driven directly by mclk<x>, but gated to prevent toggling during asynchronous accesses, or when no transfers are occurring.
Read data output by the memory device is also registered on the rising edge of mclk<x>n, equivalent to the falling edge of mclk<x>, for asynchronous reads. For synchronous reads, read data is registered using the fed-back clock, fbclk_in. For synchronous and asynchronous accesses, the data is then pushed onto the read data FIFO to be returned by the AXI interface.
The internal signal read_data is included in the read transfer waveforms to indicate the clock edge on which data is registered by the SMC.
This subsection describes:
Table 2.3 lists the settings for the opmode Register.
Table 2.3. Asynchronous read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 0 | 3’b000 | - | - | - | - | - | - |
Table 2.4 lists the settings for the sram_cycles Register.
Table 2.4. Asynchronous read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0011 | - | 3’b001 | - | - | - | - |
Figure 2.13 shows a single asynchronous read transfer with an initial access time, tRC, of 3 cycles and an output enable assertion delay, tCEOE, of one cycle.
Table 2.5 lists the settings for the opmode Register.
Table 2.5. Asynchronous read in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 0 | 3’b000 | - | - | - | 1 | - | - |
Table 2.6 lists the settings for the sram_cycles Register.
Table 2.6. Asynchronous read in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0111 | - | 3’b101 | - | - | - | - |
Figure 2.14 shows a single asynchronous read transfer in multiplexed SRAM mode, with tRC = 7, and tCEOE = 5.
In multiplexed mode, both address and data are output by the SMC on the data_out bus. Read data is accepted on the data_in bus. The address is still driven onto the address bus in multiplexed mode. This enables you to use the upper address bits for memories that require more address bits than data bits.
Table 2.7 lists the settings for the opmode Register.
Table 2.7. Asynchronous write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | - | - | 0 | 3’b000 | - | - | - | - |
Table 2.8 lists the settings for the sram_cycles Register.
Table 2.8. Asynchronous write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | - | 4’b0100 | - | 3’b010 | - | - | 0 |
Figure 2.15 shows an asynchronous write with a write cycle time tWC of four cycles and a we_n assertion duration, tWP, of two cycles.
The timing parameter tWP controls the deassertion of we_n. You can use it to vary the hold time of cs_n, addr and data. This differs from the read case where the timing parameter tCEOE controls the delay in the assertion of oe_n. Additionally, we_n is always asserted one cycle after cs_n to ensure the address bus is valid.
Table 2.9 lists the settings for the opmode Register.
Table 2.9. Asynchronous write in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | - | - | 0 | 3’b000 | 0 | 0 | - | - |
Table 2.10 lists the settings for the sram_cycles Register.
Table 2.10. Asynchronous write in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | - | 4’b0111 | - | 3’b100 | - | - | 0, see Figure 2.16. 1, |
Figure 2.16 shows an asynchronous write in multiplexed mode when the we_time bit is 0. tWC is seven cycles, tWP is four cycles, and the we_time bit programs the assertion of we_n to occur two clock cycles after cs_n goes LOW.
Figure 2.17 shows an asynchronous write in multiplexed mode when the we_time bit is 1. tWC is seven cycles, tWP is four cycles, and the we_time bit programs the assertion of we_n to occur when cs_n goes LOW.
Table 2.11 lists the settings for the opmode Register.
Table 2.11. Page read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 0 | <page length> | - | - | - | - | - | 1 |
Table 2.12 lists the settings for the sram_cycles Register.
Table 2.12. Page read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0011 | - | 3’b010 | - | 3’b001 | - | - |
Figure 2.18 shows a page read access, with an initial access time, tRC, of three cycles, an output enable assertion delay, tCEOE, of two cycles, and a page access time, tPC, of one cycle.
You enable Page mode in the SMC by setting the opmode Register for the relevant chip to asynchronous reads, and the burst length to the page size.
Multiplexed mode page accesses are not supported.
Table 2.13 lists the settings for the opmode Register.
Table 2.13. Synchronous burst read opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 1 | <burst length> | - | - | - | 1 | - | - |
Table 2.14 lists the settings for the sram_cycles Register.
Table 2.14. Synchronous burst read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0100 | - | 3’b010 | - | - | - | - |
Figure 2.19 shows a burst read with the wait output of the memory used to delay the transfer.
Synchronous memories have a configuration register enabling wait to be asserted either on the same clock cycle as the delayed data, or a cycle early. The SMC only supports wait being asserted one cycle early, enabling wait to be initially sampled with the fed-back clock and then with mclk before being used by the FSM. This enables the easiest timing closure. Additionally, you must configure the memory for wait to be active LOW.
In synchronous operation, the SMC relies on the wait signal being de-asserted HIGH to indicate that the memory can finish the transfer. When in synchronous mode, some memories do not de-assert the wait signal during non-array read transfers. Non-array read transfers are typically status register reads. To avoid stalling the system with these memories, in synchronous mode you must not perform non-array read transfers with the memory and SMC.
You must set tRC to a value that enables wait_reg_mclk to stabilize. See Figure 2.19.
Table 2.15 lists the settings for the opmode Register.
Table 2.15. Synchronous burst read in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 1 | <burst length> | - | - | - | - | - | - |
Table 2.16 lists the settings for the sram_cycles Register.
Table 2.16. Synchronous burst read in multiplexed mode read sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0100 | - | 3’b010 | - | - | - | - |
Figure 2.20 shows the same synchronous read burst transfer as Figure 2.19, but in multiplexed mode.
Table 2.17 lists the settings for the opmode Register.
Table 2.17. Synchronous burst write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | - | - | 1 | <burst length> | - | 1 | - | - |
Table 2.18 lists the settings for the sram_cycles Register.
Table 2.18. Synchronous burst write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | - | 4’b0100 | - | 3’b001 | - | - | - |
Figure 2.21 shows a synchronous burst write transfer that is delayed by the wait signal. You must configure the memory to assert wait one cycle early and with an active LOW priority. The wait signal is again registered with the fed-back clock and mclk before being used. The wait signal is used in the mclk domain to the memory interface FSM.
Synchronous memories have a configuration register enabling wait to be asserted either on the same clock cycle as the delayed data, or a cycle early. The SMC only supports wait being asserted one cycle early, enabling wait to be initially sampled with the fed-back clock and then with mclk before being used by the FSM. This enables the easiest timing closure. Additionally, you must configure the memory for wait to be active LOW.
You must set tWC to a value that enables wait_reg_mclk to stabilize. See Figure 2.21.
Table 2.19 lists the settings for the opmode Register.
Table 2.19. Synchronous burst write in multiplexed mode opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | - | - | 1 | <burst length> | - | 1 | - | - |
Table 2.20 lists the settings for the sram_cycles Register.
Table 2.20. Synchronous burst write in multiplexed mode sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | - | 4’b0100 | - | 3’b001 | - | - | - |
Figure 2.22 shows the same synchronous burst write as Figure 2.21, but in multiplexed mode.
Table 2.21 lists the settings for the opmode Register.
Table 2.21. Synchronous read and asynchronous write opmode Register settings
| Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | burst_align |
| Value | - | 1 | 3’b001 | 0 | 3’b000 | 0 | 1 | 0 | - |
Table 2.20 lists the settings for the sram_cycles Register.
Table 2.22. Synchronous read and asynchronous write sram_cycles Register settings
| Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr | we_time |
| Value | 4’b0100 | 4’b0110 | 3’b010 | 3’b001 | - | 3’b011 | - |
Figure 2.23 shows the turnaround time tTR, enforced between synchronous read and asynchronous write. The turnaround time is enforced between:
reads followed by writes
writes followed by reads
read following a read from a different chip select.
For tRC:
when using memory devices that are not wait-enabled, you must program tRC to be the number of clock cycles required before valid data is available following the assertion of cs_n
when using memory devices that are wait-enabled, you must program tRC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:
t_RC = 3 + t_CEOE
t_CEOE is only required if wait is asserted when oe_n goes LOW.
For tWC:
when using memory devices that are not wait-enabled, you must program tWC to be the number of clock cycles required before the first data is written, following the assertion of cs_n
when using memory devices that are wait-enabled, you must program tWC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:
t_WC = 3
If a memory device is configured so that there are two or less clock cycles between the assertion of wait and data being required then you must program tWC as if the memory device is not wait-enabled.
During repeated access to the same chip, the SMC can keep chip select asserted. To support memories that require chip select to be deasserted periodically, you can program the refresh_period_<x> Register to set a maximum number of consecutive memory bursts. You can set the number of consecutive bursts from one to 15, inclusive. See refresh_period_0 Register and refresh_period_1 Register.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Functional operation > SRAM interface timing diagrams |