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Table A.13 lists the AXI-R channel signals.
Table A.13. AXI-R channel signals
| Signal | Type | Source/ destination | Description |
|---|---|---|---|
| rid[7:0] | Output | Slave | Read ID tag. This signal is the ID tag of the read transfer. The rid value must match the arid value of the read transaction to which the slave is responding. |
| rdata[PORTWIDTH-1:0][1] | Output | Slave | Read data. The read data bus can be 32 or 64 bits wide. |
| rresp[1:0] | Output | Slave | Read response. This signal indicates the status of the read transfer. The permitted responses are OKAY and EXOKAY. |
| rlast | Output | Slave | Read last. This signal indicates the last transfer in a read burst. |
| rready | Input | Master | Read ready. This signal indicates that the master can accept the read data and response information: 0 = master not ready 1= master ready. |
| rvalid | Output | Slave | Read valid. This signal indicates that valid read data is available: 0 = read data not available 1 = read data available. |
[1] PORTWIDTH is the data width of the AXI interface in bits. | |||
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > AXI interface signals > Read data (AXI-R) channel signals |