| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
 PDF version | |
| Home > Signal Descriptions > AXI interface signals > AXI low-power interface signals |
| |||
| Home > Signal Descriptions > AXI interface signals > AXI low-power interface signals | |||
Table A.14 lists the optional low-power interface signals.
Table A.14. AXI low-power interface signals
| Signal | Type | Source/ destination | Description |
|---|---|---|---|
| cclken | Input | Bus clock | Clock enable. |
| csysreq | Input | Memory manager | System low-power request. This signal is a request from the system clock controller for the peripheral to enter a low-power state. |
| csysack | Output | Peripheral device | Low-power request acknowledgement. This signal is the acknowledgement from a peripheral of a system low-power state request. |
| cactive | Output | Peripheral device | Clock active. This signal indicates that the peripheral requires its clock signal: 0 = peripheral clock not required 1 = peripheral clock required. |
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > AXI interface signals > AXI low-power interface signals |