PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual 1.1.1. Features of the SMC (PL350 series)

1.1.1. Features of the SMC (PL350 series)

The SMC provides the following features:

You can configure the SMC to support the following options:
- Maximum NAND memory data widths of 8-bit or 16-bit.
- Maximum SRAM memory data widths of 8-bit, 16-bit, or 32-bit.
- AXI data width of 32-bit or 64-bit.
- Up to four chip selects per memory interface.
- Configurable command, read data, and write data FIFO depths.
- An additional pipeline stage within the format logic enables higher AXI clock frequencies at the cost of an additional clock cycle of latency.
- Configurable number of outstanding exclusive accesses supported.
- Optional 2-bit detection, 1-bit correction Error Correction Code (ECC) block for single-level cell (SLC) NAND memories.
Table 1.1 and Table 1.2 list the supported memory widths and AXI data widths. You can program the memory width for each chip select, with the maximum available being the configured width, and the minimum being one quarter of the AXI data width.
Table 1.1. SRAM memory widths and AXI data widths
Memory width AXI data width
32-bit 64-bit
8-bit Y N
16-bit Y Y
32-bit Y Y
Table 1.2. NAND memory widths and AXI data widths
Memory width AXI data width
32-bit 64-bit
8-bit Y Y
16-bit Y Y
Support for ARM Architecture Version 6 (ARMv6) exclusive access transfers to SRAM.
Programmable interrupt generation to indicate NAND flash status.
Programmable cycle timings, and memory width per chip select.
Programmable address cycles and command values for NAND flash accesses enabling operation with a variety of NAND devices.
Atomic switching of memory device and controller operating modes.
Support for the PrimeCell EBI (PL220) that enables sharing of external address and data bus pins between memory controller interfaces.
Support for AXI low-power interface.
Support for a remap signal for each interface.
Support for multiple clock domains and configurable to be synchronous or asynchronous.

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Memory width	AXI data width
Memory width	32-bit	64-bit
8-bit	Y	N
16-bit	Y	Y
32-bit	Y	Y

Memory width	AXI data width
Memory width	32-bit	64-bit
8-bit	Y	Y
16-bit	Y	Y