PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual 3.3.11. nand

3.3.11. nand_cycles Register

There is an instance of this register for each NAND chip supported. You cannot read the read-only nand_cycles Register in the Reset state. Figure 3.16 shows the register bit assignments.

Figure 3.16. nand_cycles Register bit assignments

Table 3.12 lists the register bit assignments.

Table 3.12. nand_cycles Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved, read undefined.
[23:20]	t_rr	busy to re_n for NAND chip configurations. Minimum permitted value = 0.
[19:17]	t_ar	ID read time for NAND chip configurations. Minimum permitted value = 0.
[16:14]	t_clr	Status read time for NAND chip configurations. Minimum permitted value = 0.
[13:11]	t_wp	we_n de-assertion delay. Minimum permitted value = 1.
[10:8]	t_rea	re_n assertion delay for NAND chip configurations. Minimum permitted value = 1.
[7:4]	t_wc	Write cycle time. Minimum permitted value = 2.
[3:0]	t_rc	Read cycle time. Minimum permitted value = 2.

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