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This section describes:
The following types of hazard exist:
Read after read (RAR)
Write after write (WAW)
Read after write (RAW)
Write after read (WAR).
The AXI specification defines that RAW and WAR ordering is determined by the master, whereas RAR and WAW ordering is enforced by the slave. If an AXI master requires ordering between reads and writes to certain memory locations, it must wait for a write response before issuing a read from a location it has written to (RAW). It must also wait for read data before issuing a write to a location it has read from (WAR). The SMC ensures the ordering of read transfers from a single master is maintained (RAR), and additionally, that the ordering of write transfers from a single master is maintained (WAW).
RAR hazards only occur in configurations that have two memory interfaces.
The SMC can reorder reads from different masters that connect to different memory interfaces. This situation is likely to occur, for example, in an SMC (PL353) configuration, when one master is accessing an SRAM memory interface clocked at 133MHz, and another master is accessing the NAND memory interface clocked at 50MHz. Read data from the SRAM memory is available before data from the NAND memory. This enables the SMC to potentially return read data out of order. The SMC contains internal hazard checking to ensure the AXI reads from a single master have the order maintained.
WAW hazards only occur in configurations that have two memory interfaces.
As for RAR hazards, writes to different memory interfaces are able to complete out of order. This enables the write responses to be returned out of order. The SMC internal hazard checking logic ensures only writes from different masters are completed out of order.
In addition to reads and writes, exclusive reads and writes are supported in accordance with the AMBA AXI Protocol Specification.
Successful exclusive accesses have an EXOKAY response. All other accesses, including exclusive fail accesses, receive an OKAY response.
Exclusive access monitors implement the exclusive access functionality. Each monitor can track a single exclusive access. The number of monitors is a configurable option.
If an exclusive write fails, the data mask for the write is forced LOW, so that the data is not written.
When monitoring an exclusive access, the address of any write from another master is compared with the monitored address to check that the location is not being updated.
For the purposes of monitoring, address comparison is made using a bit mask derived in the following fashion.
Consider the byte addresses accessed by a transaction. All the least significant bits, up to and including, the most significant bit that vary between those addresses are set to logic zero in the mask. All the stable address bits above this point are set to logic one.
Example 2.1 provides information about three transactions.
Example 2.1.
Address = 0x100, size = WORD,
length = 1, ID = 0.
Address = 0x104,
size = WORD, length = 2, ID = 1.
Address
= 0x100, size = WORD, length = 1, ID = 0.
The write transaction accesses the address range 0x104-0x10B.
Therefore, address bit 3 is the most significant bit that varies
between byte addresses. The bit mask is therefore formed so that
address bits 3 down to 0 are not compared. This has the effect that
the masked write, as far as the monitoring logic has calculated,
has accessed the monitored address. Therefore the exclusive write
is marked as having failed.
Table 2.1 lists the address comparison steps:
Table 2.1. Address comparison steps example
| Step | Binary | Hex | |
|---|---|---|---|
| 1 | Monitored address | b000100000000 | 0x100 |
| 2 | Write address | b000100000100 | 0x104 |
| 3 | Write accesses | b000100000100 | 0x104 |
| b000100000101 | 0x105 | ||
| b000100000110 | 0x106 | ||
| b000100000111 | 0x107 | ||
| b000100001000 | 0x108 | ||
| b000100001001 | 0x109 | ||
| b000100001010 | 0x10A | ||
| b000100001011 | 0x10B | ||
| 4 | Generate a comparison mask | b111111110000 | 0xFF0 |
| 5 | Monitored address ANDed with mask | b000100000000 | 0x100 |
| 6 | Write Address ANDed with mask | b000100000000 | 0x100 |
| 7 | Compare steps 5 and 6 | ||
| 8 | Mark exclusive write as failed |
This example shows how the logic can introduce false-negatives in exclusive access monitoring, because in reality the write has not accessed the monitored address. The implementation has been chosen to reduce design complexity, but always provides safe behavior.
When calculating the address region accessed by the write,
the burst type is always taken to be INCR. Therefore, a wrapped
transaction in Example 2.1 that wraps
down to 0x0 rather than cross the boundary, is
treated in the same way. This is the same for a fixed burst that
does not cross the boundary or wrap down to 0x0.
This section describes:
The SMC defines two phases of commands when transferring data to or from NAND flash.
Commands and optional address information are written to the NAND flash. The command and address can be associated with either a data phase operation to write to or read from the array, or a status/ID register transfer.
Data is either written to or read from the NAND flash. This data can be either data transferred to or from the array, or status/ID register information.
The SMC uses information contained in the AXI address bus, either awaddr[ ] or araddr[ ] signals, to determine whether the AXI transfer is a command or data phase access.
This information contained in the address bus additionally determines:
the value of the command
the number of address cycles
the chip select to be accessed.
During a command phase transfer, the address to be written to the NAND memory is transferred to the SMC using the AXI write channel.
The size of the AXI transfer for data phase transfers must be larger than the width of the memory interface.
Table 2.2 lists the fields of awaddr[ ] and araddr[ ] signals that control a NAND flash transfer.
Table 2.2. NAND AXI address setup
| AXI address | Command phase | Data phase |
|---|---|---|
| [31:24] | Chip address | Chip address |
| [23] | NoOfAddCycles_2 | Reserved |
| [22] | NoOfAddCycles_1 | Reserved |
| [21] | NoOfAddCycles_0 | ClearCS |
| [20] | End command valid | End command valid [1] |
| [19] | 0 | 1 |
| [18:11] | End command | End command [2] |
| [10:3] | Start command | [10] ECC Last[9:3] Reserved |
| [2:0] | Reserved [3] | Reserved [3] |
[1] For a read data phase transaction, the end command valid must be 0. [2] End command data is ignored if end command valid is not true. [3] The bottom three bits of a NAND access determine the valid data byte lanes, in the same way as for a standard AXI access. | ||
A command phase transfer is always performed as an AXI write. The AXI awaddr[ ] bus, and Table 2.2 contain the following information:
The number of address cycles can be any value from zero to seven. Generally, up to five cycles are used during an array read or write, but a maximum of seven enables support for future devices.
The NAND command is used to initiate the required operation, for example:
page read
page program
random page read
status or ID register read.
The value of the second command, if required. This command is executed when all address cycles have completed. For example, some NAND memories require an additional command, following the address cycles, for a page read.
Indicates whether the end command must be issued to the NAND flash.
Each address cycle consumes eight bits of address information. This is transferred to the SMC through the AXI write channel.
To ease system integration, the SMC supports the use of multiple AXI write transactions to transfer address information. The following restrictions apply in this case:
The AXI address [31:3] bits must not change between transactions. The first transaction must be doubleword aligned.
All other address information must be the same, with the exception of transaction length.
Data must be transferred in incrementing, consecutive accesses, that is, not wrapping, fixed, or sparse.
Extra or unused beats in the last transaction must have write strobes disabled.
Total number of beats must be less than the write FIFO depth.
Transfers data to or from the NAND flash, and can be performed as either an AXI read or write, depending on the required operation. The araddr[ ] or awaddr[ ] bus, and Table 2.2 contain this information:
The value of a command that is issued following the data transfer. This is required by some memories to indicate a page program following input of write data.
End commands are not supported for read data phase transfers.
Indicates whether the end command must be issued to NAND flash.
When set, the chip select for a NAND flash is de-asserted on completion of this command. When not set, the chip select remains asserted.
When set, this bit indicates to the ECC block that the current command is the last access to the NAND page. It is ignored if the ECC block is not enabled. See Error Correction Code operation.
A NAND flash data phase program or read operation is expected to require multiple AXI transfers because of the large page size of NAND memories. Some memory devices require the chip select to remain asserted for the duration of a page access. The SMC keeps the chip select asserted for the:
When nand_csl is tied HIGH.
When the ClearCS is not set. The SMC asserts the chip select while multiple AXI transfers transfer data to or from the NAND flash internal page. On the last AXI transfer, you can de-assert the chip select by setting the ClearCS bit.
Using the optional ClearCS functionality or the nand_csl signal causes the SMC to keep requesting the EBI, until the chip select is cleared. You must take care, at the system level, to ensure that this does not cause a deadlock when using the EBI.
Figure 2.7 and Figure 2.8 show the steps taken to perform NAND flash page read and page program operations respectively.
You can poll for either a page program or page read completion in two ways:
Poll the raw_int_status bit in the memc_status Register to determine when the memory busy_<x> output has gone HIGH, indicating a page program completion or read data ready.
In a system with multiple NAND flash devices connected to the SMC. The busy outputs are wire-ANDed to produce the single busy_<x> input to the SMC, that only transitions HIGH when all devices have completed. You can determine the status register of each NAND chip by reading the individual device status register.
Figure 2.9 shows the steps taken to perform a NAND flash status register read.
The process boxes that Figure 2.9 shows are defined as:
awaddr =
(start_cmd = STATUS_READ_CMD
end_cmd = 0x0
end_valid = 0x0
addr_cycles = 0x0)
Ensure burst length is 1, awlen = 0x0.
wdata = (don’t care).
araddr = (ClearCS = 0x1).
Ensure burst length is 1, arlen = 0x0.
The transfer size is eight or sixteen, arsize = 0x0 or 0x1.
rdata = NAND flash status output.
Certain NAND flash devices can support multiple status register reads without reissuing the STATUS_READ_CMD. In this case, you can modify the flow that Figure 2.9 describes to include multiple data phase transfers for each command phase transfer.
The upper byte of the address read or write bus, araddr[31:24] or awaddr[31:24], and the value of the address_match[ ] and address_mask[ ] buses determine the chip select being accessed. To select a memory device either:
araddr[31:24] & address_mask[ ] must equal address_match[ ]
awaddr[31:24] & address_mask[ ] must equal address_match[ ]
The values for the address_mask and address_match buses must be set so that no address maps onto more than one chip, otherwise the behavior of the SMC is undefined. If an AXI access does not map to any memory device then the SMC performs an asynchronous transfer on memory interface 0 with all chip selects deasserted. After the transfer completes, the SMC provides an OKAY response.
This section describes:
The AXI programmer’s view is a flat area of memory. The full range of AXI operations are supported.
The upper byte of the address read or write bus, araddr[31:24] or awaddr[31:24], and the value of the address_match[ ] and address_mask[ ] buses determine the chip select being accessed. To select a memory device either:
araddr[31:24] & address_mask[ ] must equal address_match[ ]
awaddr[31:24] & address_mask[ ] must equal address_match[ ]
The values for the address_mask and address_match buses must be set so that no address maps onto more than one chip, otherwise the behavior of the SMC is undefined. If an AXI access does not map to any memory device then the SMC performs an asynchronous transfer on memory interface 0 with all chip selects deasserted. After the transfer completes, the SMC provides an OKAY response.
In addition to reads and writes, exclusive reads and writes are supported in accordance with the AMBA AXI Protocol v1.0 Specification.
Successful exclusive accesses have an EXOKAY response. All other accesses, including exclusive fail accesses, receive an OKAY response.
The arcache, awcache, arprot and awprot signals are included in the AXI interface list for completeness only. The SMC does not use the information transferred by these signals.
To produce the address presented to the memory device, the AXI address is aligned to the memory width. This is done because the AXI address is a byte-aligned address, whereas the memory address is a memory-width-aligned address.
During initial configuration of a memory device, the memory mode register can be accessed with a sequence of transfers to specific addresses. You must take into consideration the shifting performance by the SMC when accessing memory mode registers.
The SMC provides a programmable option for controlling the formatting of memory transfers with respect to memory burst boundaries, through the burst_align bit of the opmode registers.
When set, the burst_align bit causes memory bursts to be aligned to a memory burst boundary. This setting is intended for use with memories that use the concept of internal pages. This can be an asynchronous page mode memory, or a synchronous PSRAM. If an AXI burst crosses a memory burst boundary, the SMC partitions the AXI transfer into multiple memory bursts, terminating a memory transfer at the burst boundary. Ensure the page size is an integer multiple of the burst length, to avoid a memory burst crossing a page boundary.
When the burst_align bit is not set, the SMC ignores the memory burst boundary when mapping AXI commands onto memory commands. This setting is intended for use with devices such as NOR flash. These devices have no concept of pages.
The SMC enables you to program the memory burst length on an individual chip basis, from length 1 to 32 beats, or a continuous burst. The length of memory bursts are however automatically limited by the size of the read or write data FIFOs.
For read transfers, the maximum memory burst length on the memory interface is the depth of the read data FIFO. For writes, the maximum burst length is dependent on:
the beat size
of the AXI transfer, asize
the memory data bus width, mw
the depth of the write data FIFO depth, wfifo_depth.
The formula to determine the maximum memory write burst length is:
Memory write burst length = ((1<<asize) x
wfifo_depth) / (1<<mw)
The SMC enables the lowest SRAM chip select, normally chip 0, to be bootable. To enable SRAM memory to be bootable, the SRAM interface does not require any special functionality, other than knowing the memory width of the memory concerned. This is indicated by a top-level tie-off. To enable the SMC to work with the slowest memories, the timing registers reset to the worst-case values. When the remap_<x> signal is HIGH, the memory with the bootable chip select is set by the sram_mw_<x>[1:0] tie-off signals.
Additionally, while the SMC input remap_<x> is
HIGH, the bootable chip is aliased to base address 0x0.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Functional operation > Format block |