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The memory manager module is responsible for controlling the state of the SMC and updating the chip configuration registers.
This subsection describes:
The SMC accepts requests to enter the low-power state through either the AXI low-power interface, or the APB register interface.
The SMC does not enter the power-down state until it has received an idle indication from all areas of the peripheral, that is:
there is no valid transfer held in the format block
there are no valid transfers held in the AXI interface
all FIFOs are empty
all memory interface blocks are IDLE.
When the low-power state is entered, the AXI outputs awready, arready, and wready are driven LOW to prevent any new AXI transfers being accepted. No new AXI transfers are accepted until the SMC has been moved out of low-power state. The SMC does not request to move out of low-power state, and never refuses a power-down request.
The SMC provides a mechanism for synchronizing the switching of operating modes with that of the memory device.
The set_cycles Register and set_opmode Register act as holding registers for new operating parameters until the SMC detects the memory device has switched modes. This enables a memory device to be made to change its operating mode while still being accessed.
Figure 2.10 shows
the memory manager containing a bank of registers for each memory
chip supported by the SMC configuration. The manager register bank consists
of all the timing parameters chip<x>_cycles,
and access modes chip<x>_opmode. These
are required for the SMC to correctly time any type of access to
a supported memory type.
The APB registers set_cycles and set_opmode act as holding registers, the configuration registers within the manager are only updated if either:
the Direct Command Register indicates only a register update is taking place
the direct_cmd Register indicates a mode register access either using the direct_cmd Register or using the AXI interface and the command has completed.
The chip configuration registers are available as read-only registers in the address map of the APB interface.
The SMC enables code to be executed from the memory while simultaneously, from the software perspective, moving the same chip to a different operating mode. This is achieved by synchronizing the update of the chip configuration registers from the holding registers with the dispatch of the memory configuration register write.
The SMC provides two mechanisms for simultaneously updating the controller and memory configuration registers. These are:
For memories that use an input pin to indicate that a write is intended for the configuration register, for example some PSRAM devices, the write mechanism can be implemented using the Direct Command Register. Figure 2.11 shows the sequence of events.
For memories that require a sequence of read and write commands, for example, most NOR flash devices use the AXI interface, with the write data bus used to indicate when the last transfer has completed and when it is safe for the SMC to update the chip configuration registers. Figure 2.12 shows the sequence of events.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0380G |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Functional operation > Memory manager operation |