PrimeCell ® StaticMemory Controller (PL350 series) Technical Reference Manual

Revision: r2p1

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the SMC (PL350 series)
1.1.1. Features of the SMC (PL350 series)
1.1.2. AXI interface attributes
1.2. Supported devices
1.3. Product revisions
2. Functional Overview
2.1. Functional description
2.1.1. AXI slave interface
2.1.2. APB slave interface
2.1.3. Format
2.1.4. Memory manager
2.1.5. Memory interface
2.1.6. Pad interface
2.2. Functional operation
2.2.1. Operating states
2.2.2. Clocking and resets
2.2.3. Miscellaneous signals
2.2.4. APB slave interface operation
2.2.5. Format block
2.2.6. Memory manager operation
2.2.7. Interrupts operation
2.2.8. Memory interface operation
2.2.9. SRAM interface timing diagrams
2.2.10. NAND interface timingdiagrams
2.2.11. Error Correction Codeoperation
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Interface Configuration Register
3.3.3. Set Configuration Register
3.3.4. Clear Configuration Register
3.3.5. Direct Command Register
3.3.6. set_cycles Register
3.3.7. set_opmode Register
3.3.8. refresh_period_0 Register
3.3.9. refresh_period_1 Register
3.3.10. sram_cycles Register
3.3.11. nand_cycles Register
3.3.12. opmode Register
3.3.13. user_status Register
3.3.14. user_config Register
3.3.15. ECC Status Register
3.3.16. ECC Configuration Register
3.3.17. ECC Command1 Register
3.3.18. ECC Command2 Register
3.3.19. ECC Address0 Register
3.3.20. ECC Address1 Register
3.3.21. ECC Value (0 … 4) Register
3.3.22. Peripheral Identification Registers0-3
3.3.23. PrimeCell Identification Registers0-3
4. Programmer’s Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration Outputs Register
5. Device Driver Requirements
5.1. Memory initialization
5.2. NAND transactions
6. Configurations
6.1. SMC (PL351)
6.1.1. Functional overview
6.1.2. Programmer’s model
6.1.3. Programmer’s model for test
6.1.4. Signal descriptions
6.2. SMC (PL352)
6.2.1. Functional overview
6.2.2. Programmer’s model
6.2.3. Programmer’s model for test
6.2.4. Signal descriptions
6.3. SMC (PL353)
6.3.1. Functional overview
6.3.2. Programmer’s model
6.3.3. Programmer’s model for test
6.3.4. Signal descriptions
6.4. SMC (PL354)
6.4.1. Functional overview
6.4.2. Programmer’s model
6.4.3. Programmer’s model for test
6.4.4. Signal descriptions
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.2.1. SRAM miscellaneous signals
A.2.2. NAND miscellaneous signals
A.2.3. Interrupt miscellaneous reset signals
A.2.4. Tie-off miscellaneous signals
A.2.5. User programmable signals
A.3. AXI interface signals
A.3.1. Write address (AXI-AW) channel signals
A.3.2. Write data (AXI-W) channel signals
A.3.3. Buffered write (AXI-B) response channelsignals
A.3.4. Read address (AXI-AR) channel signals
A.3.5. Read data (AXI-R) channelsignals
A.3.6. AXI low-power interfacesignals
A.4. APB signals
A.5. Pad interface signals
A.5.1. SRAM
A.5.2. NAND
A.6. EBI signals

List of Figures

1. Key to timing diagram conventions
1.1. SMC interfaces
1.2. SMC (PL351) examplesystem
1.3. SMC (PL353) example system
2.1. SMC block diagram
2.2. AXI slave interface signals
2.3. APB external signals
2.4. SRAM interface
2.5. NAND interface
2.6. aclk domain FSM
2.7. NAND flash page read operations
2.8. NAND flash page program operations
2.9. NAND flash status register read
2.10. Chip configuration registers
2.11. Device pin mechanism
2.12. Software mechanism
2.13. Asynchronous read
2.14. Asynchronous read in multiplexedmode
2.15. Asynchronous write
2.16. Asynchronous write in multiplexedmode when we_time is zero
2.17. Asynchronous write in multiplexedmode when we_time is one
2.18. Page read
2.19. Synchronous burst read
2.20. Synchronous burst read in multiplexedmode
2.21. Synchronous burst write
2.22. Synchronous burst write in multiplexedmode
2.23. Synchronous read and asynchronouswrite
2.24. NAND flash address input
2.25. NAND flash read
2.26. Address latch to data phase command
2.27. Busy synchronization to data phasecommand
2.28. Command latched to data phase command
2.29. Read data phase to command phase
2.30. ECC block structure
2.31. ECC state diagram
2.32. Basic operation
2.33. Every block is written
2.34. Not every block written, random access
2.35. Full jumping
2.36. addressing mode ignore_add_8 withextra blocks
3.1. Register map
3.2. Chip<n> configuration registermap
3.3. User configuration register map
3.4. ECC register map
3.5. PrimeCell configuration registermap
3.6. memc_status Register bit assignments
3.7. memif_cfg Register bit assignments
3.8. memc_cfg_set Register bit assignments
3.9. memc_cfg_clr Register bit assignments
3.10. direct_cmd Register bit assignments
3.11. set_cycles Register bit assignments
3.12. set_opmode Register bit assignments
3.13. refresh_period_0 Register bit assignments
3.14. refresh_period_1 Register bit assignments
3.15. sram_cycles Register bit assignments
3.16. nand_cycles Register bit assignments
3.17. opmode Register bit assignments
3.18. user_status Register bit assignments
3.19. user_config Register bit assignments
3.20. ecc_status Register bit assignments
3.21. ecc_memcfg Register bit assignments
3.22. ecc_memcommand1 Register bit assignments
3.23. ecc_memcommand2 Register bit assignments
3.24. ecc_addr0 Register bit assignments
3.25. ecc_addr1 Register bit assignments
3.26. ecc_value Register bit assignments
3.27. periph_id Register bit assignments
3.28. pcell_id Register bit assignments
4.1. Integration test register map
4.2. int_cfg Register bit assignments
4.3. Int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
5.1. SMC and memory initialization sheet1 of 2
5.2. SMC and memory initialization sheet2 of 2
5.3. NAND read sheet 1 of 2
5.4. NAND read sheet 2 of 2
5.5. NAND write sheet 1 of 2
5.6. NAND write sheet 2 of 2

List of Tables

1.1. SRAM memory widths and AXI data widths
1.2. NAND memory widths and AXI data widths
1.3. Attribute formats
2.1. Address comparison steps example
2.2. NAND AXI address setup
2.3. Asynchronous read opmode Register settings
2.4. Asynchronous read sram_cycles Register settings
2.5. Asynchronous read in multiplexed mode opmode Register settings
2.6. Asynchronous read in multiplexed mode sram_cycles Registersettings
2.7. Asynchronous write opmode Register settings
2.8. Asynchronous write sram_cycles Register settings
2.9. Asynchronous write in multiplexed mode opmode Register settings
2.10. Asynchronous write in multiplexed mode sram_cycles Register settings
2.11. Page read opmode Register settings
2.12. Page read sram_cycles Register settings
2.13. Synchronous burst read opmode Register settings
2.14. Synchronous burst read sram_cycles Register settings
2.15. Synchronous burst read in multiplexed mode opmode Registersettings
2.16. Synchronous burst read in multiplexed mode read sram_cycles Registersettings
2.17. Synchronous burst write opmode Register settings
2.18. Synchronous burst write sram_cycles Register settings
2.19. Synchronous burst write in multiplexed mode opmode Registersettings
2.20. Synchronous burst write in multiplexed mode sram_cycles Register settings
2.21. Synchronous read and asynchronous write opmode Register settings
2.22. Synchronous read and asynchronous write sram_cycles Register settings
2.23. NAND flash address input settings
2.24. NAND flash address input example awaddr fields
2.25. NAND flash read settings
2.26. NAND flash page read example araddr fields
2.27. Address latch to data phase settings
2.28. Busy synchronization to data phase settings
2.29. Command latched to data phase settings
2.30. Data phase to command phase settings
2.31. Normal mode addressing
2.32. Second mode addressing
3.1. Register summary
3.2. memc_status Register bit assignments
3.3. memif_cfg Register bit assignments
3.4. memc_cfg_set Register bit assignments
3.5. memc_cfg_clr Register bit assignments
3.6. direct_cmd Register bit assignments
3.7. set_cycles Register bit assignments
3.8. set_opmode Register bit assignments
3.9. refresh_period_0 Register bit assignments
3.10. refresh_period_1 Register bit assignments
3.11. sram_cycles Register bit assignments
3.12. nand_cycles Register bit assignments
3.13. opmode Register bit assignments
3.14. user_status Register bit assignments
3.15. user_config Register bit assignments
3.16. ecc_status Register bit assignments
3.17. ecc_memcfg Register bit assignments
3.18. ecc_memcommand1 Register bit assignments
3.19. ecc_memcommand2 Register bit assignments
3.20. ecc_addr0 Register bit assignments
3.21. ecc_addr1 Register bit assignments
3.22. ecc_value Register bit assignments
3.23. periph_id Register bit assignments
3.24. periph_id_0 Register bit assignments
3.25. periph_id_1 Register bit assignments
3.26. periph_id_2 Register bit assignments
3.27. periph_id_3 Register bit assignments
3.28. pcell_id Register bit assignments
3.29. pcell_id_0 Register bit assignments
3.30. pcell_id_1 Register bit assignments
3.31. pcell_id_2 Register bit assignments
3.32. pcell_id_3 Register bit assignments
4.1. SMC test register summary
4.2. int_cfg Register bit assignments
4.3. Int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. AXI domain clock and reset signals
A.2. Memory interface 0 clock and reset signals
A.3. Memory interface 1 clock and reset signals
A.4. SRAM miscellaneous signals
A.5. NAND miscellaneous signals
A.6. Interrupt miscellaneous reset signals
A.7. Tie-off miscellaneous signals
A.8. User programmable miscellaneous signals
A.9. AXI-AW channel signals
A.10. AXI-W data channel signals
A.11. AXI-B response channel signals
A.12. AXI-AR channel signals
A.13. AXI-R channel signals
A.14. AXI low-power interface signals
A.15. APB signals
A.16. SRAM pad interface signals
A.17. NAND pad interface signals
A.18. EBI signals

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 26August 2005 First release
Revision B 08March 2006 Updated for r1p0, configurable IP
Revision C 15June 2006 First release for r1p1
Revision D 22December 2006 First release for r1p2
Revision E 25May 2007 First release for r2p0
Revision F 20July 2007 Maintenance update for r2p0
Revision G 12 October2007 First release for r2p1
Copyright © 2005-2007 ARM Limited. All rights reserved. ARM DDI 0380G