CoreLink™ SMC-35x AXI Static Memory Controller Series Technical Reference Manual

Revision: r2p2


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographical conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the SMC-35x series
1.1.1. Features of the SMC-35x series
1.1.2. AXI interface attributes
1.2. Supported devices
1.3. Product revisions
2. Functional Description
2.1. Functional overview
2.1.1. AXI slave interface
2.1.2. APB slave interface
2.1.3. Format
2.1.4. Memory manager
2.1.5. Memory interface
2.1.6. Pad interface
2.1.7. Interrupts
2.1.8. User signals
2.2. Functional operation
2.2.1. Operating states
2.2.2. Clocking and resets
2.2.3. Miscellaneous signals
2.2.4. APB slave interface operation
2.2.5. Format block
2.2.6. Memory manager operation
2.2.7. Interrupts operation
2.2.8. Memory interface operation
2.2.9. SRAM interface timing diagrams
2.2.10. NAND interface timing diagrams
2.2.11. Error Correction Code block
3. Programmers Model
3.1. About the programmers model
3.1.1. Register map
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Interface Configuration Register
3.3.3. Set Configuration Register
3.3.4. Clear Configuration Register
3.3.5. Direct Command Register
3.3.6. Set Cycles Register
3.3.7. Set Operating Mode Register
3.3.8. Refresh Period 0 Register
3.3.9. Refresh Period 1 Register
3.3.10. SRAM Cycles Register
3.3.11. NAND Cycles Register
3.3.12. Operating Mode Status Register
3.3.13. User Status Register
3.3.14. User Config Register
3.3.15. ECC Status Register
3.3.16. ECC Configuration Register
3.3.17. ECC Command 0 Register
3.3.18. ECC Command 1 Register
3.3.19. ECC Address 0 Register
3.3.20. ECC Address 1 Register
3.3.21. ECC Block Registers
3.3.22. ECC Extra Block Register
3.3.23. Peripheral Identification Registers 0-3
3.3.24. CoreLink Identification Registers 0-3
4. Programmers Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration Outputs Register
5. Device Driver Requirements
5.1. Memory initialization
5.2. NAND transactions
6. Configurations
6.1. SMC-351
6.1.1. Functional overview
6.1.2. Programmers model
6.1.3. Programmers model for test
6.1.4. Signal descriptions
6.2. SMC-352
6.2.1. Functional overview
6.2.2. Programmers model
6.2.3. Programmers model for test
6.2.4. Signal descriptions
6.3. SMC-353
6.3.1. Functional overview
6.3.2. Programmers model
6.3.3. Programmers model for test
6.3.4. Signal descriptions
6.4. SMC-354
6.4.1. Functional overview
6.4.2. Programmers model
6.4.3. Programmers model for test
6.4.4. Signal descriptions
A. Revisions
B. Signal Descriptions
B.1. Clock and reset signals
B.2. Miscellaneous signals
B.2.1. SRAM miscellaneous signals
B.2.2. NAND miscellaneous signals
B.2.3. Interrupt signals
B.2.4. Tie-off signals
B.2.5. User signals
B.2.6. Scan test
B.3. AXI interface signals
B.3.1. Write address channel signals
B.3.2. Write data channel signals
B.3.3. Write response channel signals
B.3.4. Read address channel signals
B.3.5. Read data channel signals
B.3.6. AXI low-power interface signals
B.4. APB signals
B.5. Pad interface signals
B.5.1. SRAM
B.5.2. NAND
B.6. EBI signals

List of Figures

1. Key to timing diagram conventions
1.1. SMC interfaces
1.2. SMC-351 example system
1.3. SMC-353 example system
2.1. SMC block diagram
2.2. AXI slave interface signals
2.3. APB slave interface
2.4. SRAM interface
2.5. NAND interface
2.6. User signals
2.7. aclk domain FSM
2.8. NAND flash page read operations
2.9. NAND flash page program operations
2.10. NAND flash status register read
2.11. Chip configuration registers
2.12. Device pin mechanism
2.13. Software mechanism
2.14. Asynchronous read
2.15. Asynchronous read in multiplexed mode
2.16. Asynchronous write
2.17. Asynchronous write in multiplexed mode when we_time is zero
2.18. Asynchronous write in multiplexed mode when we_time is one
2.19. Page read
2.20. Synchronous burst read
2.21. Synchronous burst read in multiplexed mode
2.22. Synchronous burst write
2.23. Synchronous burst write in multiplexed mode
2.24. Synchronous read and asynchronous write
2.25. NAND flash address input
2.26. NAND flash read
2.27. Address latch to data phase command
2.28. Busy synchronization to data phase command
2.29. Command latched to data phase command
2.30. Read data phase to command phase
2.31. ECC block structure
2.32. ECC state diagram
2.33. Basic operation
2.34. Every block is written
2.35. Not every block written, random access
2.36. Full jumping
2.37. addressing mode ignore_add_8 with extra blocks
3.1. Register map
3.2. Chip<n> configuration register map
3.3. User configuration register map
3.4. ECC register map
3.5. CoreLink configuration register map
3.6. memc_status Register bit assignments
3.7. memif_cfg Register bit assignments
3.8. mem_cfg_set Register bit assignments
3.9. mem_cfg_clr Register bit assignments
3.10. direct_cmd Register bit assignments
3.11. set_cycles Register bit assignments
3.12. set_opmode Register bit assignments
3.13. refresh_0 Register bit assignments
3.14. refresh_1 Register bit assignments
3.15. sram_cycles Register bit assignments
3.16. nand_cycles Register bit assignments
3.17. opmode Register bit assignments
3.18. user_status Register bit assignments
3.19. user_config Register bit assignments
3.20. ecc<x>_status Register bit assignments
3.21. ecc<x>_cfg Register bit assignments
3.22. ecc<x>_memcmd0 Register bit assignments
3.23. ecc<x>_memcmd1 Register bit assignments
3.24. ecc<x>_addr0 Register bit assignments
3.25. ecc<x>_addr1 Register bit assignments
3.26. ecc<x>_block<3:0> Register bit assignments
3.27. ecc<x>_extra_block Register bit assignments
3.28. periph_id_[3:0] Register bit assignments
3.29. pcell_id Register bit assignments
4.1. Integration test register map
4.2. int_cfg Register bit assignments
4.3. Int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
5.1. SMC and memory initialization sheet 1 of 2
5.2. SMC and memory initialization sheet 2 of 2
5.3. NAND read sheet 1 of 2
5.4. NAND read sheet 2 of 2
5.5. NAND write sheet 1 of 2
5.6. NAND write sheet 2 of 2

List of Tables

1.1. SRAM memory widths and AXI data widths
1.2. NAND memory widths and AXI data widths
1.3. Attribute formats
2.1. Address comparison steps example
2.2. NAND AXI address setup
2.3. Asynchronous read opmode Register settings
2.4. Asynchronous read sram_cycles Register settings
2.5. Asynchronous read in multiplexed mode opmode Register settings
2.6. Asynchronous read in multiplexed mode sram_cycles Register settings
2.7. Asynchronous write opmode Register settings
2.8. Asynchronous write sram_cycles Register settings
2.9. Asynchronous write in multiplexed mode opmode Register settings
2.10. Asynchronous write in multiplexed mode sram_cycles Register settings
2.11. Page read opmode Register settings
2.12. Page read sram_cycles Register settings
2.13. Synchronous burst read opmode Register settings
2.14. Synchronous burst read sram_cycles Register settings
2.15. Synchronous burst read in multiplexed mode opmode Register settings
2.16. Synchronous burst read in multiplexed mode read sram_cycles Register settings
2.17. Synchronous burst write opmode Register settings
2.18. Synchronous burst write sram_cycles Register settings
2.19. Synchronous burst write in multiplexed mode opmode Register settings
2.20. Synchronous burst write in multiplexed mode sram_cycles Register settings
2.21. Synchronous read and asynchronous write opmode Register settings
2.22. Synchronous read and asynchronous write sram_cycles Register settings
2.23. NAND flash address input settings
2.24. NAND flash address input example awaddr fields
2.25. NAND flash read settings
2.26. NAND flash page read example araddr fields
2.27. Address latch to data phase settings
2.28. Busy synchronization to data phase settings
2.29. Command latched to data phase settings
2.30. Data phase to command phase settings
2.31. Normal mode addressing
2.32. Secondary mode addressing
2.33. ecc_fail bit and ecc_can_correct bit encoding
3.1. Register summary
3.2. memc_status Register bit assignments
3.3. memif_cfg Register bit assignments
3.4. mem_cfg_set Register bit assignments
3.5. mem_cfg_clr Register bit assignments
3.6. direct_cmd Register bit assignments
3.7. set_cycles Register bit assignments
3.8. set_opmode Register bit assignments
3.9. refresh_0 Register bit assignments
3.10. refresh_1 Register bit assignments
3.11. sram_cycles Register bit assignments
3.12. nand_cycles Register bit assignments
3.13. opmode Register bit assignments
3.14. user_status Register bit assignments
3.15. user_config Register bit assignments
3.16. ecc<x>_status Register bit assignments
3.17. ecc<x>_cfg Register bit assignments
3.18. ecc<x>_memcmd0 Register bit assignments
3.19. ecc<x>_memcmd1 Register bit assignments
3.20. ecc<x>_addr0 Register bit assignments
3.21. ecc<x>_addr1 Register bit assignments
3.22. ecc<x>_block<3:0> Register bit assignments
3.23. ecc<x>_extra_block Register bit assignments
3.24. Conceptual peripheral ID register bit assignments
3.25. periph_id_0 Register bit assignments
3.26. periph_id_1 Register bit assignments
3.27. periph_id_2 Register bit assignments
3.28. periph_id_3 Register bit assignments
3.29. pcell_id Register bit assignments
3.30. pcell_id_0 Register bit assignments
3.31. pcell_id_1 Register bit assignments
3.32. pcell_id_2 Register bit assignments
3.33. pcell_id_3 Register bit assignments
4.1. SMC test register summary
4.2. int_cfg Register bit assignments
4.3. Int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. Differences between issue G and issue H
B.1. Clock and reset signals
B.2. Memory interface 0 clock and reset signals
B.3. Memory interface 1 clock and reset signals
B.4. SRAM miscellaneous signals
B.5. NAND miscellaneous signals
B.6. Interrupt signals
B.7. Tie-off signals
B.8. User signals
B.9. Scan test signals
B.10. Write address channel signals
B.11. Write data channel signals
B.12. Write response channel signals
B.13. Read address channel signals
B.14. Read data channel signals
B.15. AXI low-power interface signals
B.16. APB interface signals
B.17. SRAM pad interface signals
B.18. NAND pad interface signals
B.19. EBI signals

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A26 August 2005First release
Revision B08 March 2006Updated for r1p0, configurable IP
Revision C15 June 2006First release for r1p1
Revision D22 December 2006First release for r1p2
Revision E25 May 2007First release for r2p0
Revision F20 July 2007Maintenance update for r2p0
Revision G12 October 2007First release for r2p1
Revision H11 November 2011First release for r2p2
Copyright © 2005-2007, 2009, 2011 ARM Limited. All rights reserved.ARM DDI 0380H
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