6.6. Parity error support

If your configuration implements parity error support, the features are as follows:

Figure 6.2 shows the parity support design features and stages. In stages 1 and 2 RAM writes and parity generation take place in parallel. RAM reads and parity checking take place in parallel in stages 3 and 4.

Figure 6.2. Parity support

The output signals PARITYFAIL[7:0] report parity errors. Typically, PARITYFAIL[7:0] reports parity errors 3 clock cycles after the corresponding RAM read.


This is not a precise error detection scheme. Designers can implement a precise error detection scheme by adding address register pipelines for RAMs. It is the responsibility of the designer to correctly implement this logic.

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