1.1.2. System design components

This section describes the PrimeCell components in Figure 1.1 in the following sections:

PrimeCell Generic Interrupt Controller

The PrimeCell Generic Interrupt Controller (PL390) can be attached to the Cortex-A9 uniprocessor. The Cortex-A9 MPCore contains an integrated interrupt controller that shares the same programmers model as the PL390 although there are implementation-specific differences.

See the Cortex-A9 MPCore Technical Reference Manual for a description of the Cortex-A9 MPCore Interrupt Controller.

PrimeCell Level 2 Cache Controller (PL310)

The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of improving the performance of ARM-based systems when significant memory traffic is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external memory accesses and has been optimized for use with Cortex-A9 processors and Cortex-A9 MPCore processors.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E