2.2.1. Program Flow Trace and the Program Trace Macrocell interface

In addition, the Cortex-A9 processor implements the Program Flow Trace (PFT) architecture protocol. The following sections describe the Cortex-A9 Program Trace Macrocell (PTM) interface:

About the PTM interface

PFT is an instruction-only trace protocol that uses waypoints to correlate the trace to the code image. Waypoints are changes in the program flow or events such as branches or changes in context ID that must be output to enable the trace.

See the CoreSight Cortex-A9 PFT Architecture Specification and the CoreSight Cortex-A9 PTM Technical Reference Manual for more information about tracing with waypoints.

Prohibited regions

Trace must be disabled in some regions. The prohibited regions are described in the ARM Architecture Reference Manual. The Cortex-A9 processor must determine prohibited regions for non-invasive debug in regions, including trace, performance monitoring, and PC sampling. No waypoints are generated for instructions that are within a prohibited region.

Only entry to and exit from Jazelle state are traced. A waypoint to enter Jazelle state is followed by a waypoint to exit Jazelle state.

Figure 2.2 shows the PTM interface signals.

Figure 2.2. PTM interface signals


See Appendix A Signal Descriptions and the CS Cortex-A9 Program Trace Macrocell TRM for more information.

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