A.7.1. AXI Master0 signals

The following data read/write sections describe the AXI Master0 interface signals:

Write address signals for AXI Master0

Table A.8 shows the AXI write address signals for AXI Master0.

Table A.8. AXI-AW signals for AXI Master0

NameI/OSource or destinationDescription
AWADDRM0[31:0]OAXI system devices

Address.

AWBURSTM0[1:0]O

Burst type:

b01 = INCR incrementing burst

b10 = WRAP Wrapping burst.

All other values are reserved.

AWCACHEM0[3:0]O

Cache type giving additional information about cacheable characteristics.

AWIDM0[1:0]O

Request ID

AWLENM0[3:0]OAXI system devices

The number of data transfers that can occur within each burst. Each burst can be 1-16 transfers long:

b0000 = 1 data transfer

b0001 = 2 data transfers

b0010 = 3 data transfers

b0011 = 4 data transfers.

AWLOCKM0[1:0]O

Lock type:

b00 = normal access

b01 = exclusive access

b10 = locked access.

AWPROTM0[2:0]O

Protection Type.

AWREADYM0I

Address ready.

AWSIZEM0[1:0]O

Burst size:

b000 = 8-bit transfer

b001 = 16-bit transfer

b010 = 32-bit transfer

b011 = 64-bit transfer.

AWUSERM0[8:0]O

[8] early BRESP. Used with PL310.

[7] full line of write zeros. Used with the PL310.

[6] clean eviction.

[5] level 1 eviction.

[4:1] inner attributes.

b0000 = Strongly-ordered.

b0001 = Device

b0011 = Normal Memory Non-Cacheable.

b0110 = Write-Through.

b0111 = Write-Back no Write-Allocate.

b1111 = Write-Back Write-Allocate.

[0] shared.

AWVALIDM0O

Address valid.


Write data channel signals

Table A.9 shows the AXI write data signals for AXI Master0.

Table A.9. AXI-W signals for AXI Master0

NameI/OSource or destinationDescription
WDATAM0[63:0]OAXI system devicesWrite data
WIDM0[1:0]OWrite ID
WLASTM0OWrite last indication
WREADYM0IWrite ready
WSTRBM0[7:0]OWrite byte lane strobe
WVALIDM0OWrite valid

Write response channel signals

Table A.10 shows the AXI write response signals for AXI Master0.

Table A.10. AXI-B signals for AXI Master0

NameI/OSource or destinationDescription
BIDM0[1:0]IAXI system devicesResponse ID
BREADYM0OResponse ready
BRESPM0[1:0]IWrite response
BVALIDM0IResponse valid

Read data channel signals

Table A.11 shows the AXI read address signals for AXI Master0.

Table A.11. AXI-AR signals for AXI Master0

NameI/OSource or destinationDescription
ARADDRM0[31:0]OAXI system devicesAddress.
ARBURSTM0[1:0]O

Burst type:

b01 = INCR incrementing burst

b10 = WRAP Wrapping burst.

ARCACHEM0[3:0]O

Cache type giving additional information about cacheable characteristics.

ARIDM0[1:0]ORequest ID
ARLENM0[3:0]O

The number of data transfers that can occur within each burst. Each burst can be 1-16 transfers long:

b0000 = 1 data transfer

b0001 = 2 data transfers

b0010 = 3 data transfers

b0011 = 4 data transfers.

ARLOCKM0[1:0]O

Lock type:

b00 = normal access

b01 = exclusive access

b10 = locked access.

ARPROTM0[2:0]O

Protection Type

ARREADYM0IAddress ready.
ARSIZEM0[1:0]OAXI system devices

Burst size:

b000 = 8-bit transfer

b001 = 16-bit transfer

b010 = 32-bit transfer

b011 = 64-bit transfer.

ARUSERM0[4:0]O

[4:1] Inner attributes

b0000 = Strongly-ordered

b0001 = Device

b0011 = Normal Memory Non-Cacheable

b0110 = Write-Through

b0111 = Write-Back no Write-Allocate

b1111 = Write-Back Write-Allocate.

[0] shared.

ARVALIDM0O

Address valid.


Read data channel signals

Table A.12 shows the AXI read data signals for AXI Master0.

Table A.12. AXI-R signals for AXI Master0

NameI/OSource or destinationDescription
RVALIDM0IAXI system devicesRead valid
RDATAM0[63:0]IRead data
RRESPM0[1:0]IRead response
RLASTM0IRead Last indication
RIDM0[1:0]IRead ID
RREADYM0ORead ready

AXI Master0 Clock enable signals

This section describes the AXI Master0 clock enable signals. Table A.13 shows the AXI Master0 clock enable signal.

Table A.13. AXI Master0 clock enable signal

NameI/OSourceDescription
ACLKENM0IClock controller

Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock.

See Clocking.


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