A.7.2. AXI Master1 signals

The following instruction interface sections describe the AXI Master1 interface signals:

Read data channel signals

Table A.14 shows the AXI read address signals for AXI Master1.

Table A.14. AXI-AR signals for AXI Master1

NameI/ODestinationDescription
ARADDRM1[31:0]OAXI system devicesAddress.
ARBURSTM1[1:0]O

Burst type:

b01 = INCR incrementing burst

b10 = WRAP Wrapping burst.

ARCACHEM1[3:0]O

Cache type giving additional information about cacheable characteristics.

ARIDM1[5:0]ORequest ID.
ARLENM1[3:0]O

The number of data transfers that can occur within each burst. Each burst can be 1-16 transfers long:

b0000 = 1 data transfer

b0001 = 2 data transfers

b0010 = 3 data transfers

b0011 = 4 data transfers.

ARLOCKM1[1:0]O

Lock type:

b00 = Normal access.

ARPROTM1[2:0]O

Protection Type.

ARREADYM1IAddress ready.
ARSIZEM1[1:0]OAXI system devices

Burst size:

b000 = 8-bit transfer

b001 = 16-bit transfer

b010 = 32-bit transfer

b011 = 64-bit transfer.

ARUSERM1[4:0]O

[4:1] = Inner attributes

b0000 = Strongly-ordered

b0001 = Device

b0011 = Normal Memory Non-Cacheable

b0110 = Write-Through

b0111 = Write-Back no Write-Allocate

b1111 = Write-Back Write-Allocate.

[0] = Shared.

ARVALIDM1OAddress valid.

Read data channel signals

Table A.15 shows the AXI read data signals for AXI Master1.

Table A.15. AXI-R signals for AXI Master1

NameI/OSource or destinationDescription
RVALIDM1IAXI system devicesRead valid
RDATAM1[63:0]IRead data
RRESPM1[1:0]IRead response
RLASTM1IRead Last indication
RIDM1[5:0]IRead ID
RREADYM1ORead ready

AXI Master1 Clock enable signals

This section describes the AXI Master1 clock enable signals. Table A.16 shows the AXI Master1 clock enable signals.

Table A.16. AXI Master1 clock enable signal

NameI/OSourceDescription
ACLKENM1IClock controller

Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock.

See Clocking.


See Chapter 7 Level 2 Memory Interface.

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