Cortex-A9 Technical Reference Manual: 10.5. External debug interface

10.5. External debug interface

The system can access memory-mapped debug registers through the Cortex-A9 APB slave port.

This APB slave interface supports 32-bits wide data, stalls, slave-generated aborts, and eleven address bits [12:2] mapping 2x4KB of memory. Bit[12] of PADDRDBG[12:0] selects which of the components is accessed:

Use PADDRDBG[12] = 0 to access the debug area of the Cortex-A9 processor. See Table 10.1 for debug resources memory mapping.
Use PADDRDBG[12] = 1 to access the Performance Monitoring Unit (PMU) area of the Cortex-A9 processor. See Chapter 9 Performance Monitoring Unit for PMU resources memory mapping.

The PADDRDBG31 signal indicates to the processor the source of the access.

See Appendix A Signal Descriptions for a complete list of the external debug signals.

Figure 10.4 shows the external debug interface signals.

Figure 10.4. External debug interface signals

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