9.1. About the Performance Monitoring Unit

The Cortex-A9 processor PMU provides six counters to gather statistics on the operation of the processor and memory system. Each counter can count any of the 58 events available in the Cortex-A9 processor. The PMU counters, and their associated control registers, are accessible from the internal CP15 interface as well as from the Debug APB interface.Table 9.1 shows the mappings of the PMU registers.

Table 9.1. Performance monitoring instructions and Debug APB mapping

Debug APB interface mappingCP15 instructionAccessResetName
0x000c9, 0, 13, 2RW-PMXEVCNTR0
0x004c9, 0, 13, 2RW-PMXEVCNTR1
0x008c9, 0, 13, 2RW-PMXEVCNTR2
0x00Cc9, 0, 13, 2RW-PMXEVCNTR3
0x010c9, 0, 13, 2RW-PMXEVCNTR4
0x014c9, 0, 13, 2RW-PMXEVCNTR5
0x07Cc9, 0, 13, 0 RW-PMCCNTR
0x400c9, 0, 13, 1 RW-PMXEVTYPER0
0x404c9, 0, 13, 1RW-PMXEVTYPER1
0x408c9, 0, 13, 1RW-PMXEVTYPER2
0x40Cc9, 0, 13, 1RW-PMXEVTYPER3
0x410c9, 0, 13, 1RW-PMXEVTYPER4
0x414c9, 0, 13, 1RW-PMXEVTYPER5
0xC00c9, 0 12, 1 RW0x00000000PMCNTENSET
0xC20c9, 0, 12, 2RW0x00000000PMCNTENCLR
0xC40c9, 0, 14, 1RW0x00000000PMINTENSET
0xC60c9, 0, 14, 2RW0x00000000PMINTENCLR
0xC80c9, 0, 12, 3RW-PMOVSR
0xCA0c9, 0, 12, 4WO-PMSWINC
0xE04c9, 0, 12, 0RW0x41093000PMCR

0xE08

c9, 0, 14, 0

RW[a]

0x00000000PMUSERENR
-c9, 0, 12, 5RW-PMSELR

[a] Read only in user mode.


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