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Table B.4 shows the cycle timings for multiplication instructions.

**Table B.5. Multiplication instruction cycle timings **

Instruction | Cycles | Result latency |
---|---|---|

| 2 | 4 |

| 3 | 4 for the first written register 5 for the second written register |

| 1 | 3 |

| 2 | 3 for the first written register 4 for the second written register |

| 1 | 3 |

| 2 | 4 |

| 2 | 3 for the first written register 4 for the second written register |

| 3 | 4 for the first written register 5 for the second written register |