10.3.3. Breakpoint Control Registers

The BCR is a read and write register that contains the necessary control bits for setting:

Figure 10.2 shows the bit arrangement of the BCRs.

Figure 10.2. Breakpoint Control Registers bit assignments


Table 10.4 shows how the bit values correspond with the Breakpoint Control Registers functions.

Table 10.4. Breakpoint Control Registers bit assignments

BitsNameDescription

[31:29]

-

RAZ on reads, SBZP on writes.

[28:24]

Breakpoint address mask

Breakpoint address mask.

RAZ/WI

b00000 = no mask

[23]

-

RAZ on reads, SBZP on writes.

[22:20]

M

Meaning of BVR:

b000 = instruction virtual address match

b001 = linked instruction virtual address match

b010 = unlinked context ID

b011 = linked context ID

b100 = instruction virtual address mismatch

b101 = linked instruction virtual address mismatch

b11x = reserved.

Note

BCR0[21], BCR1[21], BCR2[21], and BCR3[21] are RAZ on reads because these registers do not have context ID comparison capability.

[19:16]

Linked BRP

Linked BRP number. The binary number encoded here indicates another BRP to link this one with.

Note

  • if a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated

  • if this BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated.

[15:14]

Secure state access control

Secure state access control. This field enables the breakpoint to be conditional on the security state of the processor.

b00 = breakpoint matches in both Secure and Non-secure state

b01 = breakpoint only matches in Non-secure state

b10 = breakpoint only matches in Secure state

b11 = reserved.

[13:9]

-

RAZ on reads, SBZP on writes.

[8:5]

Byte address select

Byte address select. For breakpoints programmed to match an IVA, you must write a word-aligned address to the BVR. You can then use this field to program the breakpoint so it hits only if you access certain byte addresses.

If you program the BRP for IVA match:

b0000 = the breakpoint never hits

b0011 = the breakpoint hits if any of the two bytes starting at address BVR & 0xFFFFFFFC +0 is accessed

b1100 = the breakpoint hits if any of the two bytes starting at address BVR & 0xFFFFFFFC +2 is accessed

b1111 = the breakpoint hits if any of the four bytes starting at address BVR & 0xFFFFFFFC +0 is accessed.

If you program the BRP for IVA mismatch, the breakpoint hits where the corresponding IVA breakpoint does not hit, that is, the range of addresses covered by an IVA mismatch breakpoint is the negative image of the corresponding IVA breakpoint.

If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected.

Note

Writing a value to BCR[8:5] where BCR[8] is not equal to BCR[7], or BCR[6] is not equal to BCR[5], has Unpredictable results.

[4:3]

-

RAZ on reads, SBZP on writes.

[2:1]

SP

Supervisor access control. The breakpoint can be conditioned on the mode of the processor.

b00 = User, System, or Supervisor

b01 = privileged

b10 = User

b11 = any.

[0]

B

Breakpoint enable:

0 = breakpoint disabled, reset value

1 = breakpoint enabled.


Table 10.5 shows the meaning of the BVR bits.

Table 10.5. Meaning of BVR bits [22:20]

BVR[22:20]Meaning
b000

The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this BCR. It generates a breakpoint debug event on a joint IVA and state match.

b001

The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field. They generate a breakpoint debug event on a joint IVA, context ID, and state match.

b010

The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13 and the state of the processor against this BCR. This BRP is not linked with any other one. It generates a breakpoint debug event on a joint context ID and state match. For this BRP, BCR[8:5] must be set to b1111. Otherwise, it is Unpredictable whether a breakpoint debug event is generated.

b011

The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13. This BRP links another BRP (of the BCR[21:20]=b01 type), or WRP (with WCR[20]=b1). They generate a breakpoint or watchpoint debug event on a joint IVA or DVA and context ID match. For this BRP, BCR[8:5] must be set to b1111, BCR[15:14] must be set to b00, and BCR[2:1] must be set to b11. Otherwise, it is Unpredictable whether a breakpoint debug event is generated.

b100

The corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of the processor against this BCR. It generates a breakpoint debug event on a joint IVA mismatch and state match.

b101

The corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of the processor against this BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field. It generates a breakpoint debug event on a joint IVA mismatch, state and context ID match.

b11xReserved. The behavior is Unpredictable.

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