7.1.1. About the Cortex-A9 L2 interface

The Cortex-A9 L2 interface consists of two 64-bit wide AXI bus masters:

Table 7.1 shows the AXI master 0 interface attributes.

Table 7.1. AXI master 0 interface attributes

AttributeFormat
Write issuing capability

12, including:

  • eight noncacheable writes

  • four evictions

Read issuing capability

7, including:

  • six linefill reads.

or

  • one noncacheable read

Combined issuing capability19
Write ID capability2
Write interleave capability1
Write ID width2
Read ID capability3
Read ID width2

Table 7.2 shows the AXI master 1 interface attributes.

Table 7.2. AXI master 1 interface attributes

AttributeFormat
Write issuing capability

None

Read issuing capability

4 instruction reads

Combined issuing capability4
Write ID capabilityNone
Write interleave capabilityNone
Write ID widthNone
Read ID capability4
Read ID width2

The AXI protocol and meaning of each AXI signal are not described in this document. For more information see AMBA AXI Protocol v1.0 Specification.

Supported AXI transfers

Cortex-A9 master ports generate only a subset of all possible AXI transactions.

For write-back write-allocate transfers the supported transfers are:

  • WRAP4 64-bit for read transfers (linefills)

  • INCR4 64-bit for write transfers (evictions)

For noncacheable transactions:

  • INCR N (N:1-16) 32-bit read transfers

  • INCR N (N:1-8) 64-bit read transfers

  • INCR 1 8-bit, 16-bit, 32-bit, and 64-bit read transfers

  • INCR 1 8-bit, 16-bit, 32-bit, and 64-bit write transfers

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit exclusive read transfers

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit exclusive write transfers

  • INCR 1 32-bit read/write (locked) for swap

  • INCR 1 8-bit read/write (locked) for swap.

The following points apply to AXI transactions:

  • WRAP bursts are only read transfers, 64-bit, 4 transfers

  • INCR 1 can be any size for read or write

  • INCR burst (more than one transfer) are only 32-bit or 64-bit

  • No transaction is marked as FIXED

  • Write transfers with all byte strobes low can occur.

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