4.3. CP14 Jazelle registers

In the Cortex-A9 implementation of the Jazelle Extension:

Table 4.34 shows the CP14 Jazelle registers. All Jazelle registers are 32 bits wide.

Table 4.34. CP14 Jazelle registers summary



Jazelle Identity and Miscellaneous Functions Register
7100JOSCRRW-Jazelle Operating System Control Register
7200JMCRRW-Jazelle Main Configuration Register
7300Jazelle Parameters RegisterRW-Jazelle Parameters Register
7400Jazelle Configurable Opcode Translation Table RegisterWO-Jazelle Configurable Opcode Translation Table Register

[a] See Write operation of the JIDR for the effect of a write operation

See the ARM Architecture Reference Manual for details of the Jazelle Extension.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E