When this features is enabled, the Cortex-A9 processor can write entire non-coherent cache lines full of zero to the PL310 cache controller with a single request. This provides a performance improvement and some power savings. This feature can optimize the performance of the processor, but it requires a slave that is optimized for this special access. The requests are marked as full line of write zeros by having the associated AWUSER[7] bit set.

Setting bit[3] of the ACTLR enables this feature. See Auxiliary Control Register.

You must program the PL310 Cache Controller first, prior to enabling the feature in the Cortex-A9 processor, to support this feature. See the Pl310 Cache Controller TRM.