7.2. Optimized accesses to the L2 memory interface

This section describes optimized accesses to the L2 memory interface. These optimized accesses can generate non-AXI compliant requests on the Cortex-A9 AXI master ports. These non-AXI compliant requests must be generated only when the slaves connected on the Cortex-A9 AXI master ports can support them. The PL310 cache controller supports these kinds of requests. The following subsections describe the requests:

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E
Non-Confidential