7.2.1. Prefetch hint to the L2 memory interface

The Cortex-A9 processor can generate prefetch hint requests to the L2 memory controller. The prefetch hint requests are non-compliant AXI read requests generated by the Cortex-A9 processor which do not expect any data return.

You can generate prefetch hint requests to the L2 by:

L2 prefetch hint requests are identified by having their ARUSER[5] bit set.

No additional programming of the PL310 is required.

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