8.1. About the Preload Engine

If implemented, the PLE loads selected regions of memory into L2 using an MCRR preload channel operation. New dedicated events monitor the behavior of the memory region. Additional PL310 events can also monitor PLE behavior.

Preload blocks enter the PLE FIFO. FIFO entries are 100 bits long and include:

Preload blocks can span multiple page entries. Programmed entries can still be valid in case of context switches.

The Preload Engine handles cache line preload requests in the same way as a standard PLD request except that it uses its own TTB and ASID parameters. If there is a translation abort, the preload request is ignored and the Preload Engine issues the next request.

Not all the MMU settings are saved. The Domain, Tex-Remap, Primary Remap, Normal Remap, and Access Permission registers are not saved. As a consequence, a write operation in any of these registers causes a flush of the entire FIFO and of the active channel.Additionally, for Translation Lookaside Buffer (TLB) maintenance operations, the maintenance operation must be applied to the FIFO entries too. This is done as follows:

On Invalidate by MVA and ASID

Invalidate all entries with a matching ASID

On Invalidate by ASID

Invalidate all entries with a matching ASID

On Invalidate by MVA all ASID

Flush the entire FIFO

On Invalidate entire TLB

Flush the entire FIFO

These rules are also applicable to the PLE active channel.

The Preload Engine defines the following MCRR instruction to use with the preload blocks.

MCRR p15, 0, <Rt>,<Rt2> c11;Program new PLE channel

The number of entries in the FIFO can be set as an RTL configuration design choice. Available sizes are:

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