4.2.4. TLB Type Register

The TLBTR characteristics are:

Purpose

Returns the number of lockable entries for the TLB

Usage constraints

The TLBTR is:

  • common to the Secure and Non-secure states.

  • only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.1.

Figure 4.1 shows the TLBTR bit assignments.

Figure 4.1. TLBTR bit assignments


Table 4.2 shows the TLBTR bit assignments.

Table 4.2. TLBTR bit assignments

BitsNameDescription
[31:24]SBZ -
[23:16]ILsize Specifies the number of instruction TLB lockable entries. For the Cortex-A9 processor this is 0.
[15:8]DLsize Specifies the number of unified or data TLB lockable entries. For the Cortex-A9 processor this is 4.
[7:2]SBZ or UNP-
[1]TLB_size

1 the TLB has 128 entries,

0 the TLB has 64 entries

[0]nU

Specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs, 1.

For the Cortex-A9 processor this is 0.


To access the TLBTR, use:

MRC p15,0,<Rd>,c0,c0,3; returns TLB details
Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E
Non-Confidential