4.2.11. System Control Register

The SCTLR characteristics are:

Purpose

Provides control and configuration of:

  • memory alignment and endianness,

  • memory protection and fault behavior

  • MMU and cache enables

  • interrupts and behavior of interrupt latency

  • location for exception vectors

  • program flow prediction.

Usage constraints

The SCTLR is:

  • only accessible in privileged modes.

  • partially banked. System Control Register shows banked and secure modify only bits.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.7.

Figure 4.6 shows the SCTLR bit assignments.

Figure 4.6. SCTLR bit assignments


Table 4.8 shows the SCTLR bit assignments.

Table 4.8. SCTLR bit assignments

Bits

NameAccess

Description

[31]--SBZ.
[30]TEBanked

TE, Thumb exception enable:

0 = exceptions including reset are handled in ARM state.

1 = exceptions including reset are handled in Thumb state.

The TEINIT signal defines the reset value.

[29]AFEBanked

This is the Access Flag Enable bit.

0 = Full access permissions behavior. This is the reset value. The software maintains binary compatibility with ARMv6K behavior.

1 = Simplified access permissions behavior. The Cortex-A9 processor redefines the AP[0] bit as an access flag.

The TLB must be invalidated after changing the AFE bit.

[28]TREBanked

This bit controls the TEX remap functionality in the MMU.

0 = TEX remap disabled. This is the reset value.

1 = TEX remap enabled.

[27]NMFIRead-only

NMFI, nonmaskable The reset value is determined by CFGNMFI. The bit cannot be configured by software. This bit is read-only.

[26]--RAZ/SBZP
[25]EE bitBanked

Determines how the E bit in the CPSR is set on an exception:

0 = CPSR E bit is set to 0 on an exception. CFGEND sets the reset value.

1 = CPSR E bit is set to 1 on an exception.

This value also indicates the endianness of the translation table data for translation table look-ups.

0 = little-endian

1 = big-endian.

[24]--

RAZ/WI

[23:22]

-

-RAO/SBOP
[21]--

RAZ/WI

[20:19]--RAZ/SBZP
[18]--RAO/SBOP
[17]HA-

RAZ/WI

Hardware management access flag disabled.

[16]--RAO/SBOP
[15]--RAZ/SBZP
[14]RRSecure modify only

Replacement strategy for caches, BTAC, and micro TLBs. This bit is R/W in Secure state and Read-only in Non-secure state.

0 = Random replacement. This is the reset value.

1 = Round-robin replacement.

[13]VBanked

Vectors bit.

This bit selects the base address of the exception vectors:

0 = Normal exception vectors, base address 0x00000000. The Security Extensions are implemented, so this base address can be re-mapped.

1 = High exception vectors, Hivecs, base address 0xFFFF0000. This base address is never remapped.

At reset the value for the secure version if this bit is taken from VINITHI.

[12]

I bit

Banked

Determines if instructions can be cached at any available cache level:

0 = instruction caching disabled at all levels. This is the reset value.

1 = instruction caching enabled.

[11]

Z bit

Banked

Enables program flow prediction:

0 = program flow prediction disabled. This is the reset value.

1 = program flow prediction enabled.

[10]SW bitBanked

SWP/SWPB Enable bit:

0 = SWP and SWPB are Undefined.This is the reset value.

1 = SWP and SWPB perform normally.

[9:7]--RAZ/SBZP.
[6:3]--RAO/SBOP.
[2]

C bit

Banked

Determines if data can be cached at any available cache level:

0 = data caching disabled at all levels. This is the reset value.

1 = data caching enabled.

[1]

A bit

Banked

Enables strict alignment of data to detect alignment faults in data accesses:

0 = strict alignment fault checking disabled. This is the reset value.

1 = strict alignment fault checking enabled.

[0]

M bit

Banked

Enables the MMU:

0 = MMU disabled. This is the reset value.

1 = MMU enabled.


Attempts to read or write the SCTLR from secure or Non-secure User modes result in an Undefined instruction exception.

Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined instruction exception.

Attempts to write secure modify only bits in Non-secure privileged modes are ignored.

Attempts to read secure modify only bits return the secure bit value.

Attempts to modify read-only bits are ignored.

To access the SCTRL, use:

MRC p15, 0,<Rd>, c1, c0, 0; Read SCTLR
MCR p15, 0,<Rd>, c1, c0, 0; Write SCTLR
Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E
Non-Confidential