8.2.2. PLE Activity Status Register

The PLEASR characteristics are:


Indicates whether the PLE engine is currently active.

Usage constraints

The PLEASR is:

  • Common to Secure and Non-secure states

  • Accessible in User and Privileged modes, regardless of any configuration bit.


Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.


Figure 8-2 shows the PLEASR bit assignments.

Figure 8.2. PLEASR bit assignments

Table 8.2 shows the PLEASR bit assignments.

Table 8.2. PLEASR bit assignments


PLE Channel running

1 indicates that the Preload Engine is currently handling a PLE request.

To access the PLEASR, use:

MRC p15, 0, <Rt>, c11, c0, 2; Read PLEASR
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