4.2.15. Non-secure Access Control Register

The NSACR characteristics are:

Purpose

Sets the Non-secure access permission for coprocessors.

Usage constraints

The NSACR is:

  • only accessible in privileged modes.

  • a read and write register in Secure state

  • a read-only register in Non-secure state.

Note

This register has no effect on Non-secure access permissions for the debug control coprocessor, or the system control coprocessor.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.7.

Figure 4.10 shows the NSACR bit assignments.

Figure 4.10. NSACR bit assignments


Table 4.12 shows the NSACR bit assignments.

Table 4.12. NSACR bit assignments

Bits

Name

Description

[31:19]

-

UNK/SBZP.
[18]NS_SMP

Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state

0 = A write to Auxiliary Control Register in Non-secure state takes an undefined exception      and the SMP bit is write ignored. This is the reset value.

1= A write to Auxiliary Control Register in Non-secure state can modify the value of the     SMP bit. Other bits are write ignored.

[17]TL

Determines if lockable TLB entries can be allocated in Non-secure state:

0 = lockable TLB entries cannot be allocated. This is the reset value.

1 = lockable TLB entries can be allocated.

[16]PLE

Controls NS accesses to the Preload Engine resources:

0 = only Secure accesses to CP15 c11 are permitted. All Non-secure accesses to CP15 c11 are trapped to UNDEF. This is the default value.

1 = Non-secure accesses to the CP15 c11 domain are permitted. That is, PLE resources are available in the Non-secure state.

If the Preload Engine is not implemented this bit is RAZ/WI. See Chapter 8 Preload Engine.

[15]NSASEDIS

Disable Non-secure Advanced SIMD Extension functionality:

0 = this bit has no effect on the ability to write CPACR.ASEDIS. This is the reset value.

1 = the CPACR.ASEDIS bit when executing in Non-secure state has a fixed value of 1 and       writes to it are ignored.

See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.

[14]NSD32DIS

Disable the Non-secure use of D16-D31 of the VFP register file:

0 = this bit has no effect on the ability to write CPACR. D32DIS. This is the reset value.

1 = the CPACR.D32DIS bit when executing in Non-secure state has a fixed value of 1 and       writes to it are ignored.

See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.

[13:12]-UNK/SBZP.
[11]CP11

Determines permission to access coprocessor 11 in the Non-secure state:

0 = Secure access only. This is the reset value.

1 = Secure or Non-secure access.

[10]CP10

Determines permission to access coprocessor 10 in the Non-secure state:

0 = Secure access only. This is the reset value.

1 = Secure or Non-secure access.

[9:0]-UNK/SBZP

To access the NSACR, use:

MRC p15, 0,<Rd>, c1, c1, 2; Read NSACR data
MCR p15, 0,<Rd>, c1, c1, 2; Write NSACR data

See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.

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