8.2.3. PLE FIFO Status Register

The PLEFSR characteristics are:

Purpose

Indicates how many entries remain available in the PLE FIFO.

Usage constraints

The PLEFSR is:

  • Common to Secure and Non-secure states

  • Accessible in User and Privileged modes, regardless of any configuration bit.

NSAC.PLE controls Non-secure accesses.

Configurations

Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.

Attributes

Figure 8.3 shows the PLEFSR bit assignments.

Figure 8.3. PLESFR bit assignments


Table 8.3 shows the PLEFSR bit assignments.

Table 8.3. PLESFR bit assignments

BitsNameDescription
[31:5]--
[4:0]Available entries

Number of available entries in the PLE FIFO

This is the difference between the total number of entries in the FIFO, which is configuration-specific, and the number of entries already programmed.


Use the PLESFR to check that an entry is available before programming a new PLE channel.

To access the PLESFR, use:

MRC p15, 0, <Rt>, c11, c0, 4; Read the PLESFR
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