4.2.13. Coprocessor Access Control Register

The CPACR characteristics are:

Purpose
  • Sets access rights for the coprocessors CP11 and CP10.

  • Enables software to determine if any particular coprocessor exists in the system

Note

This register has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor.

Usage constraints

The CPACR is:

  • only accessible in privileged modes.

  • Common to Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.7.

Figure 4.8 shows the CPACR bit assignments.

Figure 4.8. CPACR bit assignments


Table 4.10 shows the CPACR bit assignments.

Table 4.10. CPACR bit assignments

BitsNameDescription
[31]ASEDIS

Disable Advanced SIMD Extension functionality

0 = This bit does not cause any instructions to be undefined.

1 = All instruction encodings identified in the ARM Architecture Reference Manual as being part of the Advanced SIMD Extensions but that are not VFPv3 instructions are undefined.

See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.

If implemented with VFP only, no NEON, RAO/WI.

If implemented without both VFP and NEON, UNK/SBZP.

[30]D32DIS

Disable use of D16-D31 of the VFP register file

0 = This bit does not cause any instructions to be undefined.

1 = All instruction encodings identified in the ARM Architecture Reference Manual as being VFPv3 instructions are undefined if they access any of registers D16-D31.

See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.

If implemented with VFP only, no NEON, RAO/WI.If implemented without both VFP and NEON, UNK/SBZP.

[29:24]-RAZ/WI.
[23:22]cp11

Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for nonexistent coprocessors.

b00 = Access denied. This is the reset value. Attempted access generates an Undefined instruction exception.

b01 = Privileged mode access only.

b10 = Reserved.

b11 = Privileged and User mode access.

[21:20]cp10

Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for nonexistent coprocessors.

b00 = Access denied. This is the reset value. Attempted access generates an Undefined instruction exception.

b01 = Privileged mode access only.

b10 = Reserved.

b11 = Privileged and User mode access.

[19:0]-RAZ/WI.

Access to coprocessors in the Non-secure state depends on the permissions set in the Non-secure Access Control Register.

Attempts to read or write the CPACR access bits depend on the corresponding bit for each coprocessor in Non-secure Access Control Register.

To access the CPACR, use:

MRC p15, 0,<Rd>, c1, c0, 2; Read Coprocessor Access Control Register
MCR p15, 0,<Rd>, c1, c0, 2; Write Coprocessor Access Control Register

You must execute an ISB immediately after an update of the CPACR. See Memory Barriers in the ARM Architecture Reference Manual. You must not attempt to execute any instructions that are affected by the change of access rights between the ISB and the register update.

To determine if any particular coprocessor exists in the system, write the access bits for the coprocessor of interest with b11. If the coprocessor does not exist in the system the access rights remain set to b00.

Note

You must enable both coprocessor 10 and coprocessor 11 before accessing any NEON or VFP system registers.

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