4.2.7. Cache Level ID Register

The CLIDR characteristics are:

Purpose

Indicates the cache levels that are implemented.

Usage constraints

The CLIDR is:

  • only accessible in privileged modes.

  • common to the Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.7.

Figure 4.4 shows the CLIDR bit assignments.

Figure 4.4. CLIDR bit assignments


Table 4.5 shows the CLIDR bit assignments.

Table 4.5. CLIDR bit assignments

BitsNameDescription
[31:30]-UNP or SBZ
[29:27]LoUb001 = Level of unification
[26:24]LoCb001 = Level of coherency
[23:21]LoUISb001 = Level of Unification Inner Shareable.
[20:18]CL 7b000 = No cache at CL 7
[17:15]CL 6b000 = No cache at CL 6
[14:12]CL 5b000 = No cache at CL 5
[11:9]CL 4b000 = No cache at CL 4
[8:6]CL 3b000 = No cache at CL 3
[5:3]CL 2b000 = No unified cache at CL 2
[2:0]CL 1b011 = Separate instruction and data caches at CL 1

To access the CLIDR, use:

MRC p15, 1,<Rd>, c0, c0, 1; Read CLIDR
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