4.2.9. Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Selects the current CCSIDR.

Usage constraints

The CSSELR is:

  • only accessible in privileged modes.

  • banked for Secure and Non-secure states

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.1.

Figure 4.5 shows the CSSELR bit assignments.

Figure 4.5. CSSELR bit assignments


Table 4.6 shows the CSSELR bit assignments.

Table 4.6. CSSELR bit assignments

BitsNameDescription
[31:4]-UNP or SBZ
[3:1]Level

Cache level selected

RAZ/WI

There is only one level of cache in the Cortex-A9 processor so the value for this field is b000.

[0]InD

1 = Instruction cache

0 = Data cache.


To access the CSSELR, use:

MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR
MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
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