A.13.4. Miscellaneous debug interface signals

Table A.28 shows the miscellaneous debug interface signals.

Table A.28. Miscellaneous debug signals

NameI/OSource or destinationDescription
COMMRXODebug comms channel

Communications channel receive.

Receive portion of Data Transfer Register full flag:

0 = empty

1 = full.

COMMTXODebug comms channel

Communications channel transmit.

Transmit portion of Data Transfer Register full flag:

0 = empty

1 = full.

DBGNOPWRDWNODebuggerDebugger has requested the Cortex-A9 processor is not powered down.
DBGSWENABLEIExternal debugger

When LOW only the external debug agent can modify debug registers.

0 = not enabled.

1 = enabled.

DBGROMADDR[31:12]ISystem configuration

Specifies bits [31:12] of the ROM table physical address.

If the address cannot be determined tie this signal off to zero.

DBGROMADDRVI

Valid signal for DBGROMADDR.

If the address cannot be determined tie this signal LOW.

DBGSELFADDR[31:15]I

Specifies bits [31:15] of the two’s complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined tie this signal off to zero.

DBGSELFADDRVI

Valid signal for DBGSELFADDR.

If the offset cannot be determined tie this signal LOW.


See Chapter 10 Debug.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E
Non-Confidential