A.13.3. CTI signals

Table A.27 shows the CTI signals.

Table A.27. CTI signals

NameI/OSource or destinationDescription
EDBGRQIExternal debugger or CoreSight interconnect

External debug request:

0 = no external debug request

1 = external debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGACKODebug acknowledge signal.

Indicates that all memory accesses issued by the Cortex-A9 processor result from operations performed by a debugger. Active HIGH.


Causes the core to exit from Debug state. It must be held HIGH until DBGRESTARTED is deasserted.

0 = not enabled

1 = enabled.


Used with DBGRESTART to move between Debug state and Normal state.

0 = not enabled

1 = enabled.

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