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This section describes memory consistency.
Memory coherency in a Cortex-A9 processor is maintained following a weakly ordered memory consistency model.
When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
| Copyright © 2008-2009 ARM. All rights reserved. | ARM DDI 0388E |
| Non-Confidential | |
| PDF version | |
| Home > Functional Description > Constraints and limitations of use |