6.1.1. Memory system

This section describes:

Cache features

The Cortex-A9 processor has separate instruction and data caches. The caches have the following features:

  • Each cache can be disabled independently, using the system control coprocessor. See System Control Register.

  • Cache replacement policy is either pseudo round-robin or pseudo random.

  • Both caches are 4-way set-associative.

  • The cache line length is eight words.

  • On a cache miss, critical word first filling of the cache is performed.

  • You can configure the instruction and data caches independently during implementation to sizes of 16KB, 32KB, or 64KB.

  • For optimum area and performance, all of the cache RAMs, and the associated tag RAMs, are designed to be implemented using standard ASIC RAM compilers.

  • To reduce power consumption, the number of full cache reads is reduced by taking advantage of the sequential nature of many cache operations. If a cache read is sequential to the previous cache read, and the read is within the same cache line, only the data RAM set that was previously read is accessed.

Instruction cache features

The instruction cache is virtually indexed and physically tagged.

Data cache features

The data cache is physically indexed and physically tagged.

Both data cache read misses and write misses are non-blocking with up to four outstanding data cache read misses and up to four outstanding data cache write misses being supported.

Store buffer

The Cortex-A9 CPU has a store buffer with four 64-bit slots with data merging capability.

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