1.6. Configurable options for the Cortex-A9 processor

Table 1.1 shows the Cortex-A9 processor RTL configurable options.

Table 1.1. Configurable options for the Cortex-A9 processor

FeatureRange of optionsDefault value
Instruction cache size 16KB, 32KB, or 64KB32KB
Data cache size 16KB, 32KB, or 64KB32KB
TLB entries64 entries or 128 entries128 entries
Jazelle Architecture ExtensionFull or trivialFull
Media Processing Engine with NEON technology Included or not[a]Not included
FPUIncluded or not[a]
PTM interfaceIncluded or not
Wrappers for power off and dormant modesIncluded or not
Support for parity error detection- Inclusion of this feature is a configuration and design decision.
Preload EngineIncluded or not

Preload Engine FIFO size[b]

16, 8, or 4 entries16 entries
ARM_BISTIncluded or not Included

[a] The MPE and FPU RTL options are mutually exclusive. If you choose the MPE option, the MPE is included along with its VFPv3-D32 FPU, and the FPU RTL option is not available in this case. When the MPE RTL option is not implemented, you can implement the VFPv3-D16 FPU by choosing the FPU RTL option.

[b] Only when the design includes the Preload Engine.

The MBIST solution must be configured to match the chosen Cortex-A9 cache sizes. In addition, the form of the MBIST solution for the RAM blocks in the Cortex-A9 design must be determined when the processor is implemented.

For details, see the Cortex-A9 MBIST Controller Technical Reference Manual.

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